Tests: Add t_uvm_hello version-based test

Author: wsnyder

submodules/verilator

@@ -5,10 +5,10 @@
 // any use, without warranty, 2019 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/);
-   initial begin
-      $write("Hello World\n");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+module t;
+  initial begin
+    $write("Hello World\n");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule

t/t_a_hello.v

@@ -12,10 +12,10 @@
 
 // verilator lint_off DECLFILENAME
 
-module t (/*AUTOARG*/);
-   initial begin
-      $write("Hello World\n");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+module t;
+  import uvm_pkg::*;
+  initial begin
+    // verilator lint_off WIDTHTRUNC
+    `uvm_info("TOP", "Hello World!", UVM_MEDIUM);
+  end
 endmodule

t/t_uvm_parse.v t/t_uvm_hello.vt/t_uvm_parse.v renamed to t/t_uvm_hello.v

@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_uvm_hello.v"
+
+uvm_git = os.path.abspath(test.t_dir + "/../submodules/uvm")
+uvm_root = os.path.abspath(test.obj_dir + "/uvm-worktree")
+
+if not os.path.exists(uvm_root):
+    test.run(cmd=[
+        "cd " + uvm_git +
+        " && git worktree prune && git worktree add --detach " + uvm_root +
+        " 2017-1.0"
+    ])
+
+test.compile(v_flags=[
+    "--binary -j 0 -Wall",  #
+    "-Wno-EOFNEWLINE",  # Temp - need to cleanup UVM repo
+    "+incdir+" + uvm_root + "/src"
+])
+
+test.execute()
+
+test.file_grep(test.run_log_filename, r'Hello World')
+
+test.passes()