Implement DPC CSR for RISC-V

riscv/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add `dpc` CSR support for RISC-V
 - Add Mtopi
 - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
 - Add `miselect` CSR

riscv/src/register.rs

@@ -131,3 +131,4 @@ mod tests;
 
 // TODO: Debug Mode Registers
 pub mod dcsr;
+pub mod dpc;

riscv/src/register/dpc.rs

@@ -0,0 +1,25 @@
+//! dpc register — Debug PC (0x7b1)
+
+read_write_csr! {
+    /// Debug PC Register
+    Dpc: 0x7b1,
+    mask: !1usize,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_dpc_alignment_mask() {
+        let dpc = Dpc::from_bits(0x1);
+        assert_eq!(dpc.bits() & 1, 0);
+    }
+
+    #[test]
+    fn test_dpc_bits_roundtrip() {
+        let dpc = Dpc::from_bits(0x12345);
+        assert_eq!(dpc.bits(), 0x12344);
+        assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits());
+    }
+}