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author
Jiang Jiang Jian
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Merge branch 'bugfix/fix_i2s_std_initializer_order_for_cpp_compiler_v5.4' into 'release/v5.4'
fix(i2s): fixed i2s_std initializer order for cpp compiler (v5.4) See merge request espressif/esp-idf!37047
2 parents 6150ea9 + b18506d commit aa97a0f

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-221
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+142
-221
lines changed

‎components/esp_driver_i2s/include/driver/i2s_pdm.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/

‎components/esp_driver_i2s/include/driver/i2s_std.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -215,8 +215,8 @@ extern "C" {
215215
#define I2S_STD_CLK_DEFAULT_CONFIG(rate) { \
216216
.sample_rate_hz = rate, \
217217
.clk_src = I2S_CLK_SRC_DEFAULT, \
218-
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
219218
.ext_clk_freq_hz = 0, \
219+
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
220220
}
221221
#endif
222222

‎components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c‎

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -986,3 +986,33 @@ TEST_CASE("I2S_asynchronous_read_write", "[i2s]")
986986

987987
TEST_ASSERT(received);
988988
}
989+
990+
#if SOC_I2S_SUPPORTS_PDM2PCM
991+
TEST_CASE("I2S_PDM2PCM_existence_test", "[i2s]")
992+
{
993+
i2s_chan_handle_t rx_handle;
994+
i2s_chan_config_t rx_chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_AUTO, I2S_ROLE_MASTER);
995+
TEST_ESP_OK(i2s_new_channel(&rx_chan_cfg, NULL, &rx_handle));
996+
997+
i2s_pdm_rx_config_t pdm_rx_cfg = {
998+
.clk_cfg = I2S_PDM_RX_CLK_DEFAULT_CONFIG(16000),
999+
.slot_cfg = I2S_PDM_RX_SLOT_PCM_FMT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_MONO),
1000+
.gpio_cfg = {
1001+
.clk = MASTER_BCK_IO,
1002+
.din = DATA_IN_IO,
1003+
.invert_flags = {
1004+
.clk_inv = false,
1005+
},
1006+
},
1007+
};
1008+
TEST_ESP_OK(i2s_channel_init_pdm_rx_mode(rx_handle, &pdm_rx_cfg));
1009+
TEST_ESP_OK(i2s_channel_enable(rx_handle));
1010+
1011+
uint8_t *r_buf[64] = {};
1012+
size_t r_bytes = 0;
1013+
// If PDM2PCM is not supported in the hardware, it will fail to read.
1014+
TEST_ESP_OK(i2s_channel_read(rx_handle, r_buf, 64, &r_bytes, 1000));
1015+
TEST_ESP_OK(i2s_channel_disable(rx_handle));
1016+
TEST_ESP_OK(i2s_del_channel(rx_handle));
1017+
}
1018+
#endif

‎components/hal/esp32c5/include/hal/i2s_ll.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -743,7 +743,6 @@ static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw)
743743
{
744744
hw->rx_conf.rx_pdm_en = false;
745745
hw->rx_conf.rx_tdm_en = true;
746-
hw->rx_pdm2pcm_conf.rx_pdm2pcm_en = false;
747746
}
748747

749748
/**

‎components/hal/esp32c61/include/hal/i2s_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/

‎components/soc/esp32c5/register/soc/i2s_reg.h‎

Lines changed: 1 addition & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -836,56 +836,6 @@ extern "C" {
836836
#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U
837837
#define I2S_TX_IIR_HP_MULT12_0_S 23
838838

839-
/** I2S_RX_PDM2PCM_CONF_REG register
840-
* I2S RX configure register
841-
*/
842-
#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x4c)
843-
/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
844-
* 1: Enable PDM2PCM RX mode. 0: DIsable.
845-
*/
846-
#define I2S_RX_PDM2PCM_EN (BIT(19))
847-
#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
848-
#define I2S_RX_PDM2PCM_EN_V 0x00000001U
849-
#define I2S_RX_PDM2PCM_EN_S 19
850-
/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
851-
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
852-
* sampling rate is 128. 0: down sampling rate is 64.
853-
*/
854-
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20))
855-
#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
856-
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U
857-
#define I2S_RX_PDM_SINC_DSR_16_EN_S 20
858-
/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
859-
* Configure PDM RX amplify number.
860-
*/
861-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU
862-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
863-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU
864-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21
865-
/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
866-
* I2S PDM RX bypass hp filter or not.
867-
*/
868-
#define I2S_RX_PDM_HP_BYPASS (BIT(25))
869-
#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
870-
#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U
871-
#define I2S_RX_PDM_HP_BYPASS_S 25
872-
/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
873-
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
874-
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
875-
*/
876-
#define I2S_RX_IIR_HP_MULT12_5 0x00000007U
877-
#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
878-
#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U
879-
#define I2S_RX_IIR_HP_MULT12_5_S 26
880-
/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
881-
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
882-
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
883-
*/
884-
#define I2S_RX_IIR_HP_MULT12_0 0x00000007U
885-
#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
886-
#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U
887-
#define I2S_RX_IIR_HP_MULT12_0_S 29
888-
889839
/** I2S_RX_TDM_CTRL_REG register
890840
* I2S TX TDM mode control register
891841
*/

‎components/soc/esp32c5/register/soc/i2s_struct.h‎

Lines changed: 2 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -295,43 +295,6 @@ typedef union {
295295
uint32_t val;
296296
} i2s_rx_recomb_dma_chn_reg_t;
297297

298-
/** Type of rx_pdm2pcm_conf register
299-
* I2S RX configure register
300-
*/
301-
typedef union {
302-
struct {
303-
uint32_t reserved_0:19;
304-
/** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
305-
* 1: Enable PDM2PCM RX mode. 0: DIsable.
306-
*/
307-
uint32_t rx_pdm2pcm_en:1;
308-
/** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
309-
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
310-
* sampling rate is 128. 0: down sampling rate is 64.
311-
*/
312-
uint32_t rx_pdm_sinc_dsr_16_en:1;
313-
/** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
314-
* Configure PDM RX amplify number.
315-
*/
316-
uint32_t rx_pdm2pcm_amplify_num:4;
317-
/** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
318-
* I2S PDM RX bypass hp filter or not.
319-
*/
320-
uint32_t rx_pdm_hp_bypass:1;
321-
/** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
322-
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
323-
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
324-
*/
325-
uint32_t rx_iir_hp_mult12_5:3;
326-
/** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
327-
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
328-
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
329-
*/
330-
uint32_t rx_iir_hp_mult12_0:3;
331-
};
332-
uint32_t val;
333-
} i2s_rx_pdm2pcm_conf_reg_t;
334-
335298
/** Type of rx_tdm_ctrl register
336299
* I2S TX TDM mode control register
337300
*/
@@ -1038,7 +1001,7 @@ typedef struct {
10381001
volatile i2s_rx_recomb_dma_chn_reg_t rx_recomb_dma_ch[4];
10391002
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
10401003
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
1041-
volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
1004+
uint32_t reserved_048;
10421005
volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
10431006
volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
10441007
volatile i2s_rx_timing_reg_t rx_timing;

‎components/soc/esp32c61/register/soc/i2s_reg.h‎

Lines changed: 1 addition & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -661,40 +661,6 @@ extern "C" {
661661
#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U
662662
#define I2S_TX_IIR_HP_MULT12_0_S 23
663663

664-
/** I2S_RX_PDM2PCM_CONF_REG register
665-
* I2S RX configure register
666-
*/
667-
#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48)
668-
/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
669-
* 1: Enable PDM2PCM RX mode. 0: DIsable.
670-
*/
671-
#define I2S_RX_PDM2PCM_EN (BIT(19))
672-
#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
673-
#define I2S_RX_PDM2PCM_EN_V 0x00000001U
674-
#define I2S_RX_PDM2PCM_EN_S 19
675-
/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
676-
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
677-
* sampling rate is 128. 0: down sampling rate is 64.
678-
*/
679-
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20))
680-
#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
681-
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U
682-
#define I2S_RX_PDM_SINC_DSR_16_EN_S 20
683-
/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
684-
* Configure PDM RX amplify number.
685-
*/
686-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU
687-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
688-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU
689-
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21
690-
/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
691-
* I2S PDM RX bypass hp filter or not.
692-
*/
693-
#define I2S_RX_PDM_HP_BYPASS (BIT(25))
694-
#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
695-
#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U
696-
#define I2S_RX_PDM_HP_BYPASS_S 25
697-
698664
/** I2S_RX_TDM_CTRL_REG register
699665
* I2S TX TDM mode control register
700666
*/

‎components/soc/esp32c61/register/soc/i2s_struct.h‎

Lines changed: 2 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -240,34 +240,6 @@ typedef union {
240240
uint32_t val;
241241
} i2s_rx_conf1_reg_t;
242242

243-
/** Type of rx_pdm2pcm_conf register
244-
* I2S RX configure register
245-
*/
246-
typedef union {
247-
struct {
248-
uint32_t reserved_0:19;
249-
/** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
250-
* 1: Enable PDM2PCM RX mode. 0: DIsable.
251-
*/
252-
uint32_t rx_pdm2pcm_en:1;
253-
/** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
254-
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
255-
* sampling rate is 128. 0: down sampling rate is 64.
256-
*/
257-
uint32_t rx_pdm_sinc_dsr_16_en:1;
258-
/** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
259-
* Configure PDM RX amplify number.
260-
*/
261-
uint32_t rx_pdm2pcm_amplify_num:4;
262-
/** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
263-
* I2S PDM RX bypass hp filter or not.
264-
*/
265-
uint32_t rx_pdm_hp_bypass:1;
266-
uint32_t reserved_26:6;
267-
};
268-
uint32_t val;
269-
} i2s_rx_pdm2pcm_conf_reg_t;
270-
271243
/** Type of rx_tdm_ctrl register
272244
* I2S TX TDM mode control register
273245
*/
@@ -973,8 +945,7 @@ typedef struct {
973945
uint32_t reserved_030[4];
974946
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
975947
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
976-
volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
977-
uint32_t reserved_04c;
948+
uint32_t reserved_048[2];
978949
volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
979950
volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
980951
volatile i2s_rx_timing_reg_t rx_timing;

‎docs/en/api-reference/peripherals/i2s.rst‎

Lines changed: 19 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@ Inter-IC Sound (I2S)
33

44
:link_to_translation:`zh_CN:[中文]`
55

6-
{IDF_TARGET_I2S_NUM:default="one", esp32="two", esp32s3="two"}
6+
{IDF_TARGET_I2S_NUM:default="one", esp32="two", esp32s3="two", esp32p4="three"}
7+
{IDF_TARGET_I2S_STD_TDM:default="standard and TDM", esp32="standard", esp32s2="standard"}
78

89
Introduction
910
------------
@@ -18,7 +19,7 @@ I2S (Inter-IC Sound) is a synchronous serial communication protocol usually used
1819

1920
{IDF_TARGET_NAME} contains {IDF_TARGET_I2S_NUM} I2S peripheral(s). These peripherals can be configured to input and output sample data via the I2S driver.
2021

21-
An I2S bus that communicates in standard or TDM mode consists of the following lines:
22+
An I2S bus that communicates in {IDF_TARGET_I2S_STD_TDM} mode consists of the following lines:
2223

2324
- **MCLK:** Master clock line. It is an optional signal depending on the slave side, mainly used for offering a reference clock to the I2S slave device.
2425
- **BCLK:** Bit clock line. The bit clock for data line.
@@ -57,10 +58,12 @@ I2S File Structure
5758

5859
**Public headers that need to be included in the I2S application are as follows:**
5960

60-
- ``i2s.h``: The header file that provides legacy I2S APIs (for apps using legacy driver).
61-
- ``i2s_std.h``: The header file that provides standard communication mode specific APIs (for apps using new driver with standard mode).
62-
- ``i2s_pdm.h``: The header file that provides PDM communication mode specific APIs (for apps using new driver with PDM mode).
63-
- ``i2s_tdm.h``: The header file that provides TDM communication mode specific APIs (for apps using new driver with TDM mode).
61+
.. list::
62+
63+
- ``i2s.h``: The header file that provides legacy I2S APIs (for apps using legacy driver).
64+
- ``i2s_std.h``: The header file that provides standard communication mode specific APIs (for apps using new driver with standard mode).
65+
:SOC_I2S_SUPPORTS_PDM: - ``i2s_pdm.h``: The header file that provides PDM communication mode specific APIs (for apps using new driver with PDM mode).
66+
:SOC_I2S_SUPPORTS_TDM: - ``i2s_tdm.h``: The header file that provides TDM communication mode specific APIs (for apps using new driver with TDM mode).
6467

6568
.. note::
6669

@@ -78,27 +81,14 @@ I2S Clock
7881
Clock Source
7982
^^^^^^^^^^^^
8083

81-
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_DEFAULT`: Default PLL clock.
82-
83-
.. only:: SOC_I2S_SUPPORTS_PLL_F160M
84-
85-
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock.
86-
87-
.. only:: SOC_I2S_SUPPORTS_PLL_F120M
88-
89-
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_120M`: 120 MHz PLL clock.
90-
91-
.. only:: SOC_I2S_SUPPORTS_PLL_F96M
92-
93-
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock.
94-
95-
.. only:: SOC_I2S_SUPPORTS_PLL_F240M
96-
97-
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_240M`: 240 MHz PLL clock.
98-
99-
.. only:: SOC_I2S_SUPPORTS_APLL
84+
.. list::
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101-
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_APLL`: Audio PLL clock, which is more precise than ``I2S_CLK_SRC_PLL_160M`` in high sample rate applications. Its frequency is configurable according to the sample rate. However, if APLL has been occupied by EMAC or other channels, the APLL frequency cannot be changed, and the driver will try to work under this APLL frequency. If this frequency cannot meet the requirements of I2S, the clock configuration will fail.
86+
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_DEFAULT`: Default PLL clock.
87+
:SOC_I2S_SUPPORTS_PLL_F160M: - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock.
88+
:SOC_I2S_SUPPORTS_PLL_F120M: - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_120M`: 120 MHz PLL clock.
89+
:SOC_I2S_SUPPORTS_PLL_F96M: - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock.
90+
:SOC_I2S_SUPPORTS_PLL_F240M: - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_240M`: 240 MHz PLL clock.
91+
:SOC_I2S_SUPPORTS_APLL: - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_APLL`: Audio PLL clock, which is more precise than ``I2S_CLK_SRC_PLL_160M`` in high sample rate applications. Its frequency is configurable according to the sample rate. However, if APLL has been occupied by EMAC or other channels, the APLL frequency cannot be changed, and the driver will try to work under this APLL frequency. If this frequency cannot meet the requirements of I2S, the clock configuration will fail.
10292

10393
Clock Terminology
10494
^^^^^^^^^^^^^^^^^
@@ -131,8 +121,8 @@ ESP32-C6 I2S 0 I2S 0 none I2S 0 none none
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ESP32-S3 I2S 0/1 I2S 0 I2S 0 I2S 0/1 none none
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ESP32-H2 I2S 0 I2S 0 none I2S 0 none none
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ESP32-P4 I2S 0~2 I2S 0 I2S 0 I2S 0~2 none none
134-
ESP32-C5 I2S 0 I2S 0 I2S 0 I2S 0 none none
135-
ESP32-C61 I2S 0 I2S 0 I2S 0 I2S 0 none none
124+
ESP32-C5 I2S 0 I2S 0 none I2S 0 none none
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ESP32-C61 I2S 0 I2S 0 none I2S 0 none none
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========= ======== ======== ======== ======== ======== ==========
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Standard Mode
@@ -847,7 +837,7 @@ Here is the table of the data received in the buffer with different :cpp:member:
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Full-duplex
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^^^^^^^^^^^
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Full-duplex mode registers TX and RX channel in an I2S port at the same time, and the channels share the BCLK and WS signals. Currently, STD and TDM communication modes supports full-duplex mode in the following way, but PDM full-duplex is not supported because due to different PDM TX and RX clocks.
840+
Full-duplex mode registers TX and RX channel in an I2S port at the same time, and the channels share the BCLK and WS signals. Currently, {IDF_TARGET_I2S_STD_TDM} communication modes supports full-duplex mode in the following way, but PDM full-duplex is not supported because due to different PDM TX and RX clocks.
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Note that one handle can only stand for one channel. Therefore, it is still necessary to configure the slot and clock for both TX and RX channels one by one.
853843

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