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Merge branch 'feat/esp32p4eco_sleep_feature_update_v5.3' into 'release/v5.3'
feat(esp_hw_support): esp32p4eco1 sleep feature update (v5.3) See merge request espressif/esp-idf!31682
2 parents 1727847 + 64ace5b commit 5c180bf

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15 files changed

+129
-36
lines changed

15 files changed

+129
-36
lines changed

‎components/esp_hw_support/include/esp_sleep.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,9 @@ typedef enum {
8383
#endif
8484
#if SOC_PM_SUPPORT_TOP_PD
8585
ESP_PD_DOMAIN_TOP, //!< SoC TOP
86+
#endif
87+
#if SOC_PM_SUPPORT_CNNT_PD
88+
ESP_PD_DOMAIN_CNNT, //!< Hight-speed connect peripherals power domain
8689
#endif
8790
ESP_PD_DOMAIN_MAX //!< Number of domains
8891
} esp_sleep_pd_domain_t;

‎components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -528,8 +528,9 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void)
528528

529529
// Wait another core start to do retention
530530
bool smp_skip_retention = false;
531+
smp_retention_state_t another_core_state;
531532
while (1) {
532-
smp_retention_state_t another_core_state = atomic_load(&s_smp_retention_state[!core_id]);
533+
another_core_state = atomic_load(&s_smp_retention_state[!core_id]);
533534
if (another_core_state == SMP_SKIP_RETENTION) {
534535
// If another core skips the retention, the current core should also have to skip it.
535536
smp_skip_retention = true;
@@ -548,9 +549,12 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void)
548549
if ((frame_critical->pmufunc & 0x3) == 0x1) {
549550
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_DONE);
550551
// wait another core trigger sleep and wakeup
551-
esp_cpu_wait_for_intr();
552552
while (1) {
553-
;
553+
// If another core's sleep request is rejected by the hardware, jumps out of blocking.
554+
another_core_state = atomic_load(&s_smp_retention_state[!core_id]);
555+
if (another_core_state == SMP_SKIP_RETENTION) {
556+
break;
557+
}
554558
}
555559
} else {
556560
// Start core1

‎components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include "freertos/FreeRTOSConfig.h"
1010
#include "sdkconfig.h"
1111

12+
#include "esp32p4/rom/cache.h"
1213
#include "soc/cache_reg.h"
1314
#define MTVT (0x307)
1415

@@ -154,7 +155,7 @@ rv_core_critical_regs_restore:
154155
/* Core 0 is wakeup core, Invalidate L1 Cache here */
155156
/* Invalidate L1 cache is required here!!! */
156157
la t0, CACHE_SYNC_MAP_REG
157-
li t1, 0x7 /* map l1 i/dcache */
158+
li t1, CACHE_MAP_L1_CACHE_MASK /* map l1 i/dcache */
158159
sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
159160
la t2, CACHE_SYNC_ADDR_REG
160161
sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */

‎components/esp_hw_support/port/esp32c5/pmu_sleep.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "soc/soc.h"
1515
#include "soc/rtc.h"
1616
#include "soc/pmu_struct.h"
17+
#include "hal/efuse_hal.h"
1718
#include "hal/lp_aon_hal.h"
1819
#include "esp_private/esp_pmu.h"
1920
#include "pmu_param.h"
@@ -280,6 +281,10 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
280281
bool pmu_sleep_finish(bool dslp)
281282
{
282283
(void)dslp;
284+
285+
// Wait eFuse memory update done.
286+
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
287+
283288
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
284289
}
285290

‎components/esp_hw_support/port/esp32c6/pmu_sleep.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,6 +347,10 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
347347
bool pmu_sleep_finish(bool dslp)
348348
{
349349
(void)dslp;
350+
351+
// Wait eFuse memory update done.
352+
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
353+
350354
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
351355
}
352356

‎components/esp_hw_support/port/esp32p4/pmu_sleep.c‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include "sdkconfig.h"
1212
#include "esp_err.h"
1313
#include "esp_attr.h"
14+
#include "esp_private/rtc_clk.h"
1415
#include "esp_private/regi2c_ctrl.h"
1516
#include "esp32p4/rom/cache.h"
1617
#include "soc/chip_revision.h"
@@ -22,6 +23,7 @@
2223
#include "soc/pau_reg.h"
2324
#include "soc/pmu_reg.h"
2425
#include "soc/pmu_struct.h"
26+
#include "hal/clk_tree_hal.h"
2527
#include "hal/lp_aon_hal.h"
2628
#include "soc/lp_system_reg.h"
2729
#include "hal/pmu_hal.h"
@@ -290,6 +292,8 @@ FORCE_INLINE_ATTR void sleep_writeback_l1_dcache(void) {
290292
while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE));
291293
}
292294

295+
static TCM_DRAM_ATTR uint32_t s_mpll_freq_mhz_before_sleep = 0;
296+
293297
TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
294298
{
295299
lp_aon_hal_inform_wakeup_type(dslp);
@@ -302,8 +306,15 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
302306
pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
303307
pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
304308

309+
// !!! Need to manually check that data in L2 memory will not be modified from now on. !!!
305310
sleep_writeback_l1_dcache();
306311

312+
// !!! Need to manually check that data in PSRAM will not be accessed from now on. !!!
313+
s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq();
314+
if (s_mpll_freq_mhz_before_sleep) {
315+
rtc_clk_mpll_disable();
316+
}
317+
307318
/* Start entry into sleep mode */
308319
pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
309320

@@ -333,6 +344,14 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
333344
pmu_sleep_shutdown_ldo();
334345
}
335346

347+
if (s_mpll_freq_mhz_before_sleep) {
348+
rtc_clk_mpll_enable();
349+
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep);
350+
}
351+
352+
// Wait eFuse memory update done.
353+
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
354+
336355
unsigned chip_version = efuse_hal_chip_revision();
337356
if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
338357
REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M

‎components/esp_hw_support/port/esp32p4/rtc_clk.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ static const char *TAG = "rtc_clk";
2828
static int s_cur_cpll_freq = 0;
2929

3030
// MPLL frequency option, 400MHz. Zero if MPLL is not enabled.
31-
static DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
31+
static TCM_DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
3232

3333
void rtc_clk_32k_enable(bool enable)
3434
{
@@ -484,13 +484,13 @@ bool rtc_dig_8m_enabled(void)
484484
}
485485

486486
//------------------------------------MPLL-------------------------------------//
487-
void rtc_clk_mpll_disable(void)
487+
TCM_IRAM_ATTR void rtc_clk_mpll_disable(void)
488488
{
489489
clk_ll_mpll_disable();
490490
s_cur_mpll_freq = 0;
491491
}
492492

493-
void rtc_clk_mpll_enable(void)
493+
TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
494494
{
495495
clk_ll_mpll_enable();
496496
}
@@ -508,7 +508,7 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
508508
s_cur_mpll_freq = mpll_freq;
509509
}
510510

511-
uint32_t rtc_clk_mpll_get_freq(void)
511+
TCM_IRAM_ATTR uint32_t rtc_clk_mpll_get_freq(void)
512512
{
513513
return s_cur_mpll_freq;
514514
}

‎components/esp_hw_support/sleep_modes.c‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,9 @@
2626
#include "freertos/FreeRTOS.h"
2727
#include "freertos/task.h"
2828
#include "soc/soc_caps.h"
29+
#include "soc/chip_revision.h"
2930
#include "driver/rtc_io.h"
31+
#include "hal/efuse_hal.h"
3032
#include "hal/rtc_io_hal.h"
3133
#include "hal/clk_tree_hal.h"
3234

@@ -862,6 +864,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
862864
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
863865
}
864866
}
867+
#elif CONFIG_IDF_TARGET_ESP32P4
868+
/* Due to esp32p4 eco0 hardware bug, if LP peripheral power domain is powerdowned in sleep, there will be a possibility of
869+
triggering the EFUSE_CRC reset, so disable the power-down of this power domain on lightsleep for ECO0 version. */
870+
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
871+
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
872+
}
865873
#endif
866874

867875
uint32_t reject_triggers = allow_sleep_rejection ? (s_config.wakeup_triggers & RTC_SLEEP_REJECT_MASK) : 0;
@@ -981,13 +989,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
981989
#endif
982990
#endif
983991

984-
#if SOC_CLK_MPLL_SUPPORTED
985-
uint32_t mpll_freq_mhz = rtc_clk_mpll_get_freq();
986-
if (mpll_freq_mhz) {
987-
rtc_clk_mpll_disable();
988-
}
989-
#endif
990-
991992
#if SOC_DCDC_SUPPORTED
992993
#if CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON
993994
if (!deep_sleep) {
@@ -1022,13 +1023,6 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
10221023
result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu, deep_sleep);
10231024
#endif
10241025

1025-
#if SOC_CLK_MPLL_SUPPORTED
1026-
if (mpll_freq_mhz) {
1027-
rtc_clk_mpll_enable();
1028-
rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), mpll_freq_mhz);
1029-
}
1030-
#endif
1031-
10321026
/* Unhold the SPI CS pin */
10331027
#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
10341028
#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
@@ -2275,6 +2269,12 @@ static uint32_t get_power_down_flags(void)
22752269
}
22762270
#endif
22772271

2272+
#if SOC_PM_SUPPORT_CNNT_PD
2273+
if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON) {
2274+
pd_flags |= PMU_SLEEP_PD_CNNT;
2275+
}
2276+
#endif
2277+
22782278
#if SOC_PM_SUPPORT_VDDSDIO_PD
22792279
if (s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option != ESP_PD_OPTION_ON) {
22802280
pd_flags |= RTC_SLEEP_PD_VDDSDIO;

‎components/esp_rom/include/esp32p4/rom/cache.h‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,16 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#ifndef _ROM_CACHE_H_
88
#define _ROM_CACHE_H_
99

10+
#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
1011
#include <stdint.h>
1112
#include "esp_bit_defs.h"
13+
#endif
1214

1315
#ifdef __cplusplus
1416
extern "C" {
@@ -86,6 +88,16 @@ extern "C" {
8688
// should NOT =
8789
#define SMMU_GID_TBIT_INDEX_HIGH (SMMU_GID_TBIT_INDEX_LOW + SMMU_GID_TBIT_NUM)
8890

91+
#define CACHE_MAP_L1_ICACHE_0 BIT(0)
92+
#define CACHE_MAP_L1_ICACHE_1 BIT(1)
93+
#define CACHE_MAP_L1_DCACHE BIT(4)
94+
#define CACHE_MAP_L2_CACHE BIT(5)
95+
96+
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
97+
#define CACHE_MAP_L1_CACHE_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE)
98+
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
99+
100+
#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
89101
typedef enum {
90102
CACHE_L1_ICACHE0 = 0,
91103
CACHE_L1_ICACHE1 = 1,
@@ -225,14 +237,6 @@ typedef enum {
225237
CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
226238
} cache_sync_t;
227239

228-
#define CACHE_MAP_L1_ICACHE_0 BIT(0)
229-
#define CACHE_MAP_L1_ICACHE_1 BIT(1)
230-
#define CACHE_MAP_L1_DCACHE BIT(4)
231-
#define CACHE_MAP_L2_CACHE BIT(5)
232-
233-
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
234-
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
235-
236240
struct cache_internal_stub_table {
237241
uint32_t (*l1_icache_line_size)(void);
238242
uint32_t (*l1_dcache_line_size)(void);
@@ -507,7 +511,7 @@ void ROM_Direct_Boot_Cache_Init(void);
507511
*
508512
* @param None
509513
*
510-
* @return 0 if mmu map is sucessfully, others if not.
514+
* @return 0 if mmu map is successfully, others if not.
511515
*/
512516
int ROM_Direct_Boot_MMU_Init(void);
513517

@@ -1517,7 +1521,7 @@ void Cache_Freeze_L2_Cache_Disable(void);
15171521
void Cache_Travel_Tag_Memory(struct cache_mode *mode, uint32_t filter_addr, void (*process)(struct tag_group_info *, int res[]), int res[]);
15181522

15191523
/**
1520-
* @brief Travel tag memory to run a call back function using 2rd tag api.
1524+
* @brief Travel tag memory to run a call back function using 2nd tag api.
15211525
* ICache and DCache are suspend when doing this.
15221526
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
15231527
* Please do not call this function in your SDK application.
@@ -1539,7 +1543,7 @@ void Cache_Travel_Tag_Memory2(struct cache_mode *mode, uint32_t filter_addr, voi
15391543
*
15401544
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
15411545
*
1542-
* @param uint32_t tag : the tag part fo a tag item, 12-14 bits.
1546+
* @param uint32_t tag : the tag part for a tag item, 12-14 bits.
15431547
*
15441548
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
15451549
*
@@ -1602,6 +1606,8 @@ int flash2spiram_rodata_offset(void);
16021606
uint32_t flash_instr_rodata_start_page(uint32_t bus);
16031607
uint32_t flash_instr_rodata_end_page(uint32_t bus);
16041608

1609+
#endif // #if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
1610+
16051611
#ifdef __cplusplus
16061612
}
16071613
#endif

‎components/esp_system/port/soc/esp32p4/reset_reason.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@
88
#include "esp_rom_sys.h"
99
#include "esp_private/system_internal.h"
1010
#include "soc/rtc_periph.h"
11+
#include "soc/chip_revision.h"
12+
#include "hal/efuse_hal.h"
1113
#include "esp32p4/rom/rtc.h"
1214

1315
static void esp_reset_reason_clear_hint(void);
@@ -57,7 +59,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
5759

5860
case RESET_REASON_CORE_EFUSE_CRC:
5961
#if CONFIG_IDF_TARGET_ESP32P4
60-
return ESP_RST_DEEPSLEEP; // TODO: IDF-9564
62+
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
63+
return ESP_RST_DEEPSLEEP;
64+
}
6165
#endif
6266
return ESP_RST_EFUSE;
6367

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