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fix(esp_hw_support): fix cpu_retention cache invalidate mask
1 parent edf14a1 commit 64ace5b

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2 files changed

+20
-13
lines changed

2 files changed

+20
-13
lines changed

components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include "freertos/FreeRTOSConfig.h"
1010
#include "sdkconfig.h"
1111

12+
#include "esp32p4/rom/cache.h"
1213
#include "soc/cache_reg.h"
1314
#define MTVT (0x307)
1415

@@ -154,7 +155,7 @@ rv_core_critical_regs_restore:
154155
/* Core 0 is wakeup core, Invalidate L1 Cache here */
155156
/* Invalidate L1 cache is required here!!! */
156157
la t0, CACHE_SYNC_MAP_REG
157-
li t1, 0x7 /* map l1 i/dcache */
158+
li t1, CACHE_MAP_L1_CACHE_MASK /* map l1 i/dcache */
158159
sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
159160
la t2, CACHE_SYNC_ADDR_REG
160161
sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */

components/esp_rom/include/esp32p4/rom/cache.h

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,16 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#ifndef _ROM_CACHE_H_
88
#define _ROM_CACHE_H_
99

10+
#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
1011
#include <stdint.h>
1112
#include "esp_bit_defs.h"
13+
#endif
1214

1315
#ifdef __cplusplus
1416
extern "C" {
@@ -86,6 +88,16 @@ extern "C" {
8688
// should NOT =
8789
#define SMMU_GID_TBIT_INDEX_HIGH (SMMU_GID_TBIT_INDEX_LOW + SMMU_GID_TBIT_NUM)
8890

91+
#define CACHE_MAP_L1_ICACHE_0 BIT(0)
92+
#define CACHE_MAP_L1_ICACHE_1 BIT(1)
93+
#define CACHE_MAP_L1_DCACHE BIT(4)
94+
#define CACHE_MAP_L2_CACHE BIT(5)
95+
96+
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
97+
#define CACHE_MAP_L1_CACHE_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE)
98+
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
99+
100+
#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
89101
typedef enum {
90102
CACHE_L1_ICACHE0 = 0,
91103
CACHE_L1_ICACHE1 = 1,
@@ -225,14 +237,6 @@ typedef enum {
225237
CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
226238
} cache_sync_t;
227239

228-
#define CACHE_MAP_L1_ICACHE_0 BIT(0)
229-
#define CACHE_MAP_L1_ICACHE_1 BIT(1)
230-
#define CACHE_MAP_L1_DCACHE BIT(4)
231-
#define CACHE_MAP_L2_CACHE BIT(5)
232-
233-
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
234-
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
235-
236240
struct cache_internal_stub_table {
237241
uint32_t (*l1_icache_line_size)(void);
238242
uint32_t (*l1_dcache_line_size)(void);
@@ -507,7 +511,7 @@ void ROM_Direct_Boot_Cache_Init(void);
507511
*
508512
* @param None
509513
*
510-
* @return 0 if mmu map is sucessfully, others if not.
514+
* @return 0 if mmu map is successfully, others if not.
511515
*/
512516
int ROM_Direct_Boot_MMU_Init(void);
513517

@@ -1517,7 +1521,7 @@ void Cache_Freeze_L2_Cache_Disable(void);
15171521
void Cache_Travel_Tag_Memory(struct cache_mode *mode, uint32_t filter_addr, void (*process)(struct tag_group_info *, int res[]), int res[]);
15181522

15191523
/**
1520-
* @brief Travel tag memory to run a call back function using 2rd tag api.
1524+
* @brief Travel tag memory to run a call back function using 2nd tag api.
15211525
* ICache and DCache are suspend when doing this.
15221526
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
15231527
* Please do not call this function in your SDK application.
@@ -1539,7 +1543,7 @@ void Cache_Travel_Tag_Memory2(struct cache_mode *mode, uint32_t filter_addr, voi
15391543
*
15401544
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
15411545
*
1542-
* @param uint32_t tag : the tag part fo a tag item, 12-14 bits.
1546+
* @param uint32_t tag : the tag part for a tag item, 12-14 bits.
15431547
*
15441548
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
15451549
*
@@ -1602,6 +1606,8 @@ int flash2spiram_rodata_offset(void);
16021606
uint32_t flash_instr_rodata_start_page(uint32_t bus);
16031607
uint32_t flash_instr_rodata_end_page(uint32_t bus);
16041608

1609+
#endif // #if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
1610+
16051611
#ifdef __cplusplus
16061612
}
16071613
#endif

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