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[CIR] Emit bitcast for equal-width types #1991

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Merged
merged 3 commits into from
Nov 25, 2025
Merged

[CIR] Emit bitcast for equal-width types #1991

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e277346
[CIR] Emit bitcast for equal-width types
Nov 17, 2025
411a74a
fix VisitAsTypeExpr to align with OG codegen
Nov 20, 2025
898b7cc
Add createCastsForTypeOfSameSize
Nov 23, 2025
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29 changes: 28 additions & 1 deletion clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -820,7 +820,34 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
mlir::Value VisitObjCDictionaryLiteral(ObjCDictionaryLiteral *E) {
llvm_unreachable("NYI");
}
mlir::Value VisitAsTypeExpr(AsTypeExpr *E) { llvm_unreachable("NYI"); }

mlir::Value VisitAsTypeExpr(AsTypeExpr *E) {
mlir::Value src = CGF.emitScalarExpr(E->getSrcExpr());
QualType qualSrcTy = E->getSrcExpr()->getType();
QualType qualDstTy = E->getType();

// Bitwidth check
unsigned srcBits = CGF.getContext().getTypeSize(qualSrcTy);
unsigned dstBits = CGF.getContext().getTypeSize(qualDstTy);
if (srcBits != dstBits) {
emitError(CGF.getLoc(E->getExprLoc()),
"source and destination must have equal bitwidths: '" +
llvm::Twine(srcBits) + "' vs '" + llvm::Twine(dstBits) +
"'");
return nullptr;
}

// No-op if already same type
mlir::Type srcTy = CGF.convertType(qualSrcTy);
mlir::Type dstTy = CGF.convertType(qualDstTy);
if (srcTy == dstTy)
return src;

// Perform the bitcast
auto loc = CGF.getLoc(E->getExprLoc());
return Builder.create<cir::CastOp>(loc, dstTy, cir::CastKind::bitcast, src);
}

mlir::Value VisitAtomicExpr(AtomicExpr *E) {
return CGF.emitAtomicExpr(E).getScalarVal();
}
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9 changes: 9 additions & 0 deletions clang/test/CIR/CodeGen/OpenCL/vec_int_as_float.cl
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Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
// RUN: %clang -target x86_64-unknown-linux-gnu -cl-std=CL3.0 -Xclang -finclude-default-header -Xclang -fclangir -emit-cir %s -o - | FileCheck %s

float4 test(int4 in)
{
return as_float4(in); // Bit reinterpretation
}

// CHECK: [[LOAD:%.*]] = cir.load align(16) %{{.*}} : !cir.ptr<!cir.vector<!s32i x 4>>, !cir.vector<!s32i x 4>
// CHECK: %{{.*}} = cir.cast bitcast [[LOAD]] : !cir.vector<!s32i x 4> -> !cir.vector<!cir.float x 4>
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