Remove decompressor state from the generated binary (#13)

* Remove decompressor state from the generated binary

* Ignore output folder

* Always init when called

* Always initialize, use a 32bit variable instead of a bool

* Fix S2, C3, H2

Author: bugadani

.gitignore

@@ -1,3 +1,3 @@
 /target
-
+/output
 esp32c3.bin

README.md

@@ -37,7 +37,7 @@ $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader outp
     ```c
     MEMORY {
         /* Start 64k into the RAM region */
-        IRAM : ORIGIN = 0x40390000, LENGTH = 0x40000
+        IRAM : ORIGIN = 0x40390000, LENGTH = 0x10000
     }
     ```
     It's important to note that the algorithm cannot be loaded at the start of RAM, because probe-rs has a header it loads prior to the algo hence the 64K offset.
@@ -47,22 +47,29 @@ $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader outp
     #[cfg(feature = "esp32c3")]
     let chip = "esp32c3";
     ```
-6. [Define `spiconfig` for your the target in `main.rs`](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+ets_efuse_get_spiconfig+path%3A*c3*&type=code)
-7. Follow the instructions above for building
+6. [Define `spiconfig` for your the target in `flash.rs`](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+ets_efuse_get_spiconfig+path%3A*c3*&type=code)
+7. Add your device to the table in `main.rs` and calculate addresses.
+8. Define your target's `STATE_ADDR`
+    ```rust
+    #[cfg(feature = "esp32c3")]
+    const STATE_ADDR: usize = 0x3FCC_0000;
+    ```
+9. Follow the instructions above for building
   - It may fail with: `rust-lld: error: undefined symbol: <symbol>`
     - In this case, you need to add the missing method in the ROM API linker script.
       - Eg. ESP32-C2 is missing `esp_rom_spiflash_attach`:
         1. [Search the symbol in esp-idf](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+esp_rom_spiflash_attach+path%3A*c2*&type=code)
         2. Add it to the ROM API linker script: `PROVIDE(esp_rom_spiflash_attach = spi_flash_attach);`
-8. Use `target-gen` _without_ the `update` flag to generate a new yaml algorithm.
-9. Update the resulting yaml file
+10. Use `target-gen` _without_ the `update` flag to generate a new yaml algorithm.
+11. Update the resulting yaml file
    1. Update `name`
    2. Update variants `name`, `type`, `core_access_options` and `memory_map`
       - The first `!Nvm`  block represents the raw flash starting at 0 and up to the maximum supported external flash (check TRM for this, usually in "System and Memory/Features")
       - Next `!Ram` block corresponds to instruction bus for internal SRAM, see Internal Memory Address Mapping of TRM
       - Next `!Ram` block corresponds to data bus for internal SRAM, see Internal Memory Address Mapping of TRM
       - Next `!Nvm` corresponds to instruction bus for external memory, see External Memory Address Mapping of TRM
       - Next `!Nvm` corresponds to data bus for external memory, see External Memory Address Mapping of TRM
-   3. Add `load_address` under `flash_algorithms` and assign the IRAM `ORIGIN` value (step 3).
+   3. Add `load_address` under `flash_algorithms` and assign the IRAM `ORIGIN` value (step 4).
+   4. Add `data_load_address` under `flash_algorithms` and assign an appropriate value residing in DRAM.
    4. Add `transfer_encoding: Miniz` under `load_address`
-9. Upstream the new updates to probe-rs.
+12. Upstream the new updates to probe-rs.

ld/esp32c2.x

@@ -1,6 +1,6 @@
 MEMORY {
     /* Start 64k into the RAM region */
-    IRAM : ORIGIN = 0x4038C000, LENGTH = 0x40800
+    IRAM : ORIGIN = 0x4038C000, LENGTH = 0x10800
 }
 
 PROVIDE(esp_rom_spiflash_attach = spi_flash_attach);

ld/esp32c3.x

@@ -1,6 +1,6 @@
 MEMORY {
     /* Start 64k into the RAM region */
-    IRAM : ORIGIN = 0x40390000, LENGTH = 0x40000
+    IRAM : ORIGIN = 0x40390000, LENGTH = 0x10000
 }
 
 PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c );

ld/esp32c6.x

@@ -1,7 +1,7 @@
 
 MEMORY {
     /* Start 64k into the RAM region */
-    IRAM : ORIGIN = 0x40810000, LENGTH = 0x40000
+    IRAM : ORIGIN = 0x40810000, LENGTH = 0x10000
 }
 
 PROVIDE(esp_rom_spiflash_attach = spi_flash_attach);

ld/esp32h2.x

@@ -1,6 +1,6 @@
 MEMORY {
     /* Start 64k into the RAM region */
-    IRAM : ORIGIN = 0x40810000, LENGTH = 0x40000
+    IRAM : ORIGIN = 0x40810000, LENGTH = 0x10000
 }
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );

ld/esp32s2.x

@@ -1,6 +1,6 @@
 MEMORY {
     /* SRAM1 + 0x4000 cache + 0x400 vectors */
-    IRAM : ORIGIN = 0x4002C400, LENGTH = 0x48000 - 0x4000 - 0x400
+    IRAM : ORIGIN = 0x4002C400, LENGTH = 0x10000
 }
 
 /**

ld/esp32s3.x

@@ -1,6 +1,6 @@
 MEMORY {
     /* SRAM2 + 0x8400 */
-    IRAM : ORIGIN = 0x40380400, LENGTH = 0x40000
+    IRAM : ORIGIN = 0x40380400, LENGTH = 0x10000
 }
 
 /* ROM function interface esp32s3.rom.ld for esp32s3

src/api_xtensa.rs

@@ -12,7 +12,7 @@ static STACK_PTR: u32 = 0x3FFE_0000;
 #[cfg(feature = "esp32s2")]
 #[no_mangle]
 // End of SRAM1. SRAM0 may be used as cache and thus may be inaccessible.
-static STACK_PTR: u32 = 0x4000_0000;
+static STACK_PTR: u32 = 0x3FFD_F000;
 
 #[cfg(feature = "esp32s3")]
 #[no_mangle]

src/main.rs

@@ -5,14 +5,53 @@
     feature(asm_experimental_arch, naked_functions)
 )]
 
+// Target memory configuration
+
+// Decompressor is 43776 bytes, reserve more in case compiler changes layout
+const _: [u8; 43776] = [0; core::mem::size_of::<Decompressor>()];
+
+// Placement:
+// - Xtensa: Pin stack top first, calculate backwards:
+//  - 32K stack
+//  - 32K for data pages
+//  - 64K for decompressor state
+// - RISC-V: At the end of memory, calculate backwards:
+//  - 64K for data pages (32K needed, but 64K is easier to calculate)
+//  - 64K for decompressor state
+//  - stack comes automatically after the loader
+
+// Xtensa   | Image IRAM  | Image DRAM  | STATE_ADDR  | data_load_addr | Stack (top)
+// ESP32-S2 | 0x4002_C400 | 0x3FFB_C400 | 0x3FFB_E000 | 0x3FFC_E000    | 0x3FFD_F000
+// ESP32-S3 | 0x4038_0400 | 0x3FC9_0400 | 0x3FCB_0000 | 0x3FCC_0000    | 0x3FCD_0000
+
+// RISC-V   | Image IRAM  | Image DRAM  | STATE_ADDR  | data_load_addr | DRAM end (avoiding cache)
+// ESP32-C2 | 0x4038_C000 | 0x3FCA_C000 | 0x3FCB_0000 | 0x3FCC_0000    | 0x3FCD_0000
+// ESP32-C3 | 0x4039_0000 | 0x3FC1_0000 | 0x3FCB_0000 | 0x3FCC_0000    | 0x3FCD_0000
+// ESP32-C6 | 0x4081_0000 | 0x4081_0000 | 0x4084_0000 | 0x4085_0000    | 0x4086_0000
+// ESP32-H2 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! has smaller RAM, only reserve 32K for data
+
+// "State" base address
+#[cfg(feature = "esp32s2")]
+const STATE_ADDR: usize = 0x3FFB_E000;
+#[cfg(feature = "esp32s3")]
+const STATE_ADDR: usize = 0x3FCB_0000;
+#[cfg(feature = "esp32c2")]
+const STATE_ADDR: usize = 0x3FCB_0000;
+#[cfg(feature = "esp32c3")]
+const STATE_ADDR: usize = 0x3FCB_0000;
+#[cfg(feature = "esp32c6")]
+const STATE_ADDR: usize = 0x4086_0000;
+#[cfg(feature = "esp32h2")]
+const STATE_ADDR: usize = 0x4082_0000;
+
+// End of target memory configuration
+
 // Define necessary functions for flash loader
 //
 // These are taken from the [ARM CMSIS-Pack documentation]
 //
 // [ARM CMSIS-Pack documentation]: https://arm-software.github.io/CMSIS_5/Pack/html/algorithmFunc.html
 
-use core::ptr::addr_of_mut;
-
 use panic_never as _;
 
 use crate::tinfl::{
@@ -25,13 +64,13 @@ mod flash;
 mod properties;
 mod tinfl;
 
+#[cfg(not(any(target_arch = "xtensa", target_arch = "riscv32")))]
+compile_error!("specify the target with `--target`");
+
 const ERROR_BASE_INTERNAL: i32 = -1000;
 const ERROR_BASE_TINFL: i32 = -2000;
 const ERROR_BASE_FLASH: i32 = -4000;
 
-#[cfg(not(any(target_arch = "xtensa", target_arch = "riscv32")))]
-compile_error!("specify the target with `--target`");
-
 #[cfg(feature = "log")]
 mod log {
 
@@ -75,63 +114,23 @@ macro_rules! dprintln {
     ($fmt:expr, $($arg:tt)*) => {};
 }
 
-static mut DECOMPRESSOR: Option<Decompressor> = None;
-
-#[cfg(feature = "esp32s2")]
-mod chip_specific {
-    use core::ops::Range;
-
-    pub const OFFSET: isize = 0x4002_8000 - 0x3FFB_8000;
-    pub const IRAM: Range<usize> = 0x4000_0000..0x4007_2000;
-}
-
-#[cfg(feature = "esp32s3")]
-mod chip_specific {
-    use core::ops::Range;
-
-    pub const OFFSET: isize = 0x4037_8000 - 0x3FC8_8000;
-    pub const IRAM: Range<usize> = 0x4000_0000..0x403E_0000;
-}
-
-// We need to access the page buffers and decompressor on the data bus, otherwise we'll run into
-// LoadStoreError exceptions. This should be removed once probe-rs can place data into the correct
-// memory region.
-fn addr_to_data_bus(addr: usize) -> usize {
-    #[cfg(any(feature = "esp32s2", feature = "esp32s3"))]
-    {
-        if chip_specific::IRAM.contains(&addr) {
-            return (addr as isize - chip_specific::OFFSET) as usize;
-        }
-    }
-
-    addr
-}
-
-unsafe fn data_bus<T>(ptr: *const T) -> *const T {
-    addr_to_data_bus(ptr as usize) as *const T
-}
-
-unsafe fn data_bus_mut<T>(ptr: *mut T) -> *mut T {
-    addr_to_data_bus(ptr as usize) as *mut T
-}
-
-unsafe fn decompressor<'a>() -> Option<&'a mut Decompressor> {
-    let decompressor = addr_of_mut!(DECOMPRESSOR);
-    let decompressor = data_bus_mut(decompressor);
+const INITED_MAGIC: u32 = 0xAAC0FFEE;
+const INITED: *mut u32 = STATE_ADDR as *mut u32;
+const DECOMPRESSOR: *mut Decompressor = (STATE_ADDR + 4) as *mut Decompressor;
 
-    decompressor.as_mut().unwrap_unchecked().as_mut()
+fn is_inited() -> bool {
+    unsafe { *INITED == INITED_MAGIC }
 }
 
 /// Setup the device for the flashing process.
 #[no_mangle]
 pub unsafe extern "C" fn Init_impl(_adr: u32, _clk: u32, _fnc: u32) -> i32 {
-    if decompressor().is_none() {
-        dprintln!("INIT");
+    dprintln!("INIT");
 
-        flash::attach();
+    flash::attach();
 
-        DECOMPRESSOR = Some(Decompressor::new());
-    }
+    *DECOMPRESSOR = Decompressor::new();
+    *INITED = INITED_MAGIC;
 
     0
 }
@@ -141,17 +140,23 @@ pub unsafe extern "C" fn Init_impl(_adr: u32, _clk: u32, _fnc: u32) -> i32 {
 /// Returns 0 on success, 1 on failure.
 #[no_mangle]
 pub unsafe extern "C" fn EraseSector_impl(adr: u32) -> i32 {
+    if !is_inited() {
+        return ERROR_BASE_INTERNAL - 1;
+    };
     flash::erase_block(adr)
 }
 
 #[no_mangle]
 pub unsafe extern "C" fn EraseChip_impl() -> i32 {
+    if !is_inited() {
+        return ERROR_BASE_INTERNAL - 1;
+    };
     flash::erase_chip()
 }
 
 #[no_mangle]
 pub unsafe extern "C" fn ProgramPage_impl(adr: u32, sz: u32, buf: *const u8) -> i32 {
-    let Some(decompressor) = decompressor() else {
+    if !is_inited() {
         return ERROR_BASE_INTERNAL - 1;
     };
 
@@ -162,24 +167,25 @@ pub unsafe extern "C" fn ProgramPage_impl(adr: u32, sz: u32, buf: *const u8) ->
 
     dprintln!("PROGRAM {} bytes @ {}", sz, adr);
 
-    // Access data through the data bus
-    let buf = data_bus(buf);
-
     let input = core::slice::from_raw_parts(buf, sz as usize);
 
-    decompressor.program(adr, input)
+    (*DECOMPRESSOR).program(adr, input)
 }
 
 #[no_mangle]
 pub unsafe extern "C" fn UnInit_impl(_fnc: u32) -> i32 {
-    let Some(decompressor) = decompressor() else {
+    if !is_inited() {
         return ERROR_BASE_INTERNAL - 1;
     };
 
-    decompressor.flush();
+    (*DECOMPRESSOR).flush();
 
     // The flash ROM functions don't wait for the end of the last operation.
-    flash::wait_for_idle()
+    let r = flash::wait_for_idle();
+
+    *INITED = 0;
+
+    r
 }
 
 pub struct Decompressor {