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bugadanibugadani
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Add ESP32-S2 (#12)
1 parent d76f7c3 commit 07b5541

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9 files changed

+159
-14
lines changed

9 files changed

+159
-14
lines changed

‎.cargo/config.toml‎

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@@ -1,4 +1,6 @@
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[alias]
2+
esp32 = "build --release --features esp32 --target xtensa-esp32-none-elf"
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esp32s2 = "build --release --features esp32s2 --target xtensa-esp32s2-none-elf"
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esp32s3 = "build --release --features esp32s3 --target xtensa-esp32s3-none-elf"
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esp32c2 = "build --release --features esp32c2 --target riscv32imc-unknown-none-elf"
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esp32c3 = "build --release --features esp32c3 --target riscv32imc-unknown-none-elf"

‎Cargo.toml‎

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@@ -13,6 +13,8 @@ ufmt = { version = "0.1.0", optional = true }
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log = ["ufmt"]
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# targets
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esp32 = []
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esp32s2 = []
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esp32s3 = []
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esp32c2 = []
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esp32c3 = []

‎README.md‎

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@@ -21,7 +21,7 @@ $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader outp
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| name | supported |
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| ------- | --------- |
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| esp32 | N |
24-
| esp32s2 | N |
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| esp32s2 | Y |
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| esp32s3 | Y |
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| esp32c2 | Y |
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| esp32c3 | Y |

‎build.rs‎

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@@ -8,6 +8,8 @@ fn main() {
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fs::copy("ld/loader.x", out_dir.join("loader.x")).unwrap();
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println!("cargo:rerun-if-changed=ld/loader.x");
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11+
#[cfg(feature = "esp32s2")]
12+
let chip = "esp32s2";
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#[cfg(feature = "esp32s3")]
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let chip = "esp32s3";
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#[cfg(feature = "esp32c2")]

‎ld/esp32s2.x‎

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@@ -0,0 +1,109 @@
1+
MEMORY {
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/* SRAM1 + 0x4000 cache + 0x400 vectors */
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IRAM : ORIGIN = 0x4002C400, LENGTH = 0x48000 - 0x4000 - 0x400
4+
}
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/**
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* ESP32-S2 ROM address table (except symbols from libgcc and libc)
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* Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796
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*
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* These are all weak symbols that could be overwritten in ESP-IDF.
11+
*/
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PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 );
14+
PROVIDE ( s_cdcacm_old_rts = 0x3ffffd34 );
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PROVIDE ( SelectSpiFunction = 0x40015d08 );
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PROVIDE ( SelectSpiQIO = 0x40015b88 );
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PROVIDE ( SendMsg = 0x40012d0c );
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PROVIDE ( send_packet = 0x40012cc8 );
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PROVIDE ( set_rtc_memory_crc = 0x40010010 );
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PROVIDE ( SetSpiDrvs = 0x40015c18 );
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PROVIDE ( sig_matrix = 0x3ffffd57 );
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PROVIDE ( software_reset = 0x40010068 );
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PROVIDE ( software_reset_cpu = 0x40010080 );
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PROVIDE ( SPI_block_erase = 0x4001623c );
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PROVIDE ( spi_cache_mode_switch = 0x40016a00 );
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PROVIDE ( SPI_chip_erase = 0x400161b8 );
27+
PROVIDE ( SPIClkConfig = 0x400170a0 );
28+
PROVIDE ( SPI_Common_Command = 0x400162e8 );
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PROVIDE ( spi_common_set_flash_cs_timing = 0x40016c0c );
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PROVIDE ( spi_dummy_len_fix = 0x40015b50 );
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PROVIDE ( SPI_Encrypt_Write = 0x400177e0 );
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PROVIDE ( SPI_Encrypt_Write_Dest = 0x400176cc );
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PROVIDE ( SPIEraseArea = 0x40017470 );
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PROVIDE ( SPIEraseBlock = 0x4001710c );
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PROVIDE ( SPIEraseChip = 0x400170ec );
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PROVIDE ( SPIEraseSector = 0x4001716c );
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PROVIDE ( esp_rom_spiflash_attach = 0x40017004 );
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PROVIDE ( spi_flash_boot_attach = 0x40016fc0 );
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PROVIDE ( spi_flash_check_suspend_cb = 0x3ffffd58 );
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PROVIDE ( SPI_flashchip_data = 0x3ffffd3c );
41+
PROVIDE ( spi_flash_set_check_suspend_cb = 0x40015b3c );
42+
PROVIDE ( SPI_init = 0x40016ce8 );
43+
PROVIDE ( SPILock = 0x40016ed4 );
44+
PROVIDE ( SPIMasterReadModeCnfig = 0x40017014 );
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PROVIDE ( SPI_page_program = 0x400165a8 );
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PROVIDE ( SPIParamCfg = 0x40017500 );
47+
PROVIDE ( SPIRead = 0x4001728c );
48+
PROVIDE ( SPI_read_data = 0x40015ed8 );
49+
PROVIDE ( SPIReadModeCnfig = 0x40016f1c );
50+
PROVIDE ( SPI_read_status = 0x40016084 );
51+
PROVIDE ( SPI_read_status_high = 0x40016284 );
52+
PROVIDE ( SPI_sector_erase = 0x400161ec );
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PROVIDE ( spi_slave_download = 0x4001998c );
54+
PROVIDE ( spi_slave_rom_check_conn = 0x40019724 );
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PROVIDE ( spi_slave_rom_init = 0x40019774 );
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PROVIDE ( spi_slave_rom_init_hw = 0x40019b5c );
57+
PROVIDE ( spi_slave_rom_intr_enable = 0x40019b3c );
58+
PROVIDE ( spi_slave_rom_rxdma_load = 0x40019da8 );
59+
PROVIDE ( spi_slave_rom_txdma_load = 0x40019e3c );
60+
PROVIDE ( SPIUnlock = 0x40016e88 );
61+
PROVIDE ( SPI_user_command_read = 0x40015fc8 );
62+
PROVIDE ( SPI_Wait_Idle = 0x40016680 );
63+
PROVIDE ( SPI_WakeUp = 0x400160f4 );
64+
PROVIDE ( SPIWrite = 0x400171cc );
65+
PROVIDE ( SPI_write_enable = 0x4001655c );
66+
PROVIDE ( SPI_Write_Encrypt_Disable = 0x40017694 );
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PROVIDE ( SPI_Write_Encrypt_Enable = 0x40017678 );
68+
PROVIDE ( SPI_write_status = 0x400162a4 );
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PROVIDE ( tdefl_compress = 0x400041dc );
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PROVIDE ( tdefl_compress_buffer = 0x40004938 );
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PROVIDE ( tdefl_compress_mem_to_mem = 0x40004a50 );
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PROVIDE ( tdefl_compress_mem_to_output = 0x40004a30 );
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PROVIDE ( tdefl_get_adler32 = 0x40004a28 );
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PROVIDE ( tdefl_get_prev_return_status = 0x40004a20 );
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PROVIDE ( tdefl_init = 0x40004954 );
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PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x40004a64 );
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PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40004a58 );
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PROVIDE ( tinfl_decompress = 0x40003000 );
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PROVIDE ( tinfl_decompress_mem_to_callback = 0x400041a8 );
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PROVIDE ( tinfl_decompress_mem_to_mem = 0x40004168 );
81+
82+
PROVIDE ( uart_tx_one_char = 0x40012b10 );
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84+
/**
85+
* SPI flash driver function, compatibility names.
86+
*/
87+
88+
PROVIDE ( g_rom_spiflash_dummy_len_plus = dummy_len_plus);
89+
PROVIDE ( g_ticks_per_us_pro = g_ticks_per_us );
90+
PROVIDE ( g_rom_flashchip = SPI_flashchip_data );
91+
PROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data );
92+
PROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg );
93+
PROVIDE ( esp_rom_spiflash_read = SPIRead );
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PROVIDE ( esp_rom_spiflash_read_status = SPI_read_status );
95+
PROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high );
96+
PROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read );
97+
PROVIDE ( esp_rom_spiflash_write = SPIWrite );
98+
PROVIDE ( esp_rom_spiflash_write_encrypted_disable = SPI_Write_Encrypt_Disable );
99+
PROVIDE ( esp_rom_spiflash_write_encrypted_enable = SPI_Write_Encrypt_Enable );
100+
PROVIDE ( esp_rom_spiflash_config_clk = SPIClkConfig );
101+
PROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO );
102+
PROVIDE ( esp_rom_spiflash_unlock = SPIUnlock );
103+
PROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector );
104+
PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock );
105+
PROVIDE ( esp_rom_spiflash_wait_idle = SPI_Wait_Idle );
106+
PROVIDE ( esp_rom_spiflash_config_readmode = SPIReadModeCnfig );
107+
PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock );
108+
PROVIDE ( esp_rom_spiflash_write_encrypted = SPI_Encrypt_Write );
109+
PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );

‎src/api_xtensa.rs‎

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@@ -4,6 +4,16 @@ use core::arch::asm;
44
// ABI, just jumping to the function address won't work. Instead, we need to use a call<N>
55
// instruction, which will set up the window increment and then jump to the function address.
66

7+
#[cfg(feature = "esp32")]
8+
#[no_mangle]
9+
// End of SRAM2
10+
static STACK_PTR: u32 = 0x3FFE_0000;
11+
12+
#[cfg(feature = "esp32s2")]
13+
#[no_mangle]
14+
// End of SRAM1. SRAM0 may be used as cache and thus may be inaccessible.
15+
static STACK_PTR: u32 = 0x4000_0000;
16+
717
#[cfg(feature = "esp32s3")]
818
#[no_mangle]
919
// End of SRAM1 - DATA_CACHE_SIZE

‎src/flash.rs‎

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@@ -27,16 +27,26 @@ extern "C" {
2727
// fn esp_rom_spiflash_lock(); // can't find in idf defs?
2828
fn esp_rom_spiflash_attach(config: u32, legacy: bool);
2929

30-
#[cfg(any(feature = "esp32c3", feature = "esp32s3"))]
30+
#[cfg(any(
31+
feature = "esp32",
32+
feature = "esp32s2",
33+
feature = "esp32s3",
34+
feature = "esp32c3",
35+
))]
3136
fn ets_efuse_get_spiconfig() -> u32;
3237
}
3338

3439
pub fn attach() {
35-
#[cfg(any(feature = "esp32c3", feature = "esp32s3"))]
36-
let spiconfig: u32 = unsafe { ets_efuse_get_spiconfig() };
40+
#[cfg(any(
41+
feature = "esp32",
42+
feature = "esp32s2",
43+
feature = "esp32s3",
44+
feature = "esp32c3",
45+
))]
46+
let spiconfig = unsafe { ets_efuse_get_spiconfig() };
3747

3848
#[cfg(any(feature = "esp32c2", feature = "esp32c6", feature = "esp32h2"))]
39-
let spiconfig: u32 = 0;
49+
let spiconfig = 0;
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4151
// TODO: raise CPU frequency
4252

‎src/main.rs‎

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@@ -77,19 +77,30 @@ macro_rules! dprintln {
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7878
static mut DECOMPRESSOR: Option<Decompressor> = None;
7979

80+
#[cfg(feature = "esp32s2")]
81+
mod chip_specific {
82+
use core::ops::Range;
83+
84+
pub const OFFSET: isize = 0x4002_8000 - 0x3FFB_8000;
85+
pub const IRAM: Range<usize> = 0x4000_0000..0x4007_2000;
86+
}
87+
88+
#[cfg(feature = "esp32s3")]
89+
mod chip_specific {
90+
use core::ops::Range;
91+
92+
pub const OFFSET: isize = 0x4037_8000 - 0x3FC8_8000;
93+
pub const IRAM: Range<usize> = 0x4000_0000..0x403E_0000;
94+
}
95+
8096
// We need to access the page buffers and decompressor on the data bus, otherwise we'll run into
8197
// LoadStoreError exceptions. This should be removed once probe-rs can place data into the correct
8298
// memory region.
8399
fn addr_to_data_bus(addr: usize) -> usize {
84-
#[cfg(feature = "esp32s3")]
100+
#[cfg(any(feature = "esp32s2", feature = "esp32s3"))]
85101
{
86-
use core::ops::Range;
87-
88-
const OFFSET: isize = 0x4037_8000 - 0x3FC8_8000;
89-
const IRAM: Range<usize> = 0x4000_0000..0x403E_0000;
90-
91-
if IRAM.contains(&addr) {
92-
return (addr as isize - OFFSET) as usize;
102+
if chip_specific::IRAM.contains(&addr) {
103+
return (addr as isize - chip_specific::OFFSET) as usize;
93104
}
94105
}
95106

‎src/properties.rs‎

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@@ -3,7 +3,6 @@ pub const PAGE_SIZE: u32 = 0x4000;
33
pub const FLASH_BLOCK_SIZE: u32 = 65536;
44

55
#[cfg(any(
6-
feature = "esp32",
76
feature = "esp32c2",
87
feature = "esp32c3",
98
feature = "esp32c6",

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