DeepSeek-V3.2-Exp #9
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instead always view the full kv_size:
- Before: returned [D_index, n_kv, ns] where n_kv could be 256
during decode with flash-attn.
- Now: always returns [D_index, kv_size, ns].
- If multiple streams are active, the code reshapes to merge the
stream dimension and then returns a 3D view to keep the KV axis
contiguous for the indexer:
- Ensures [D_index, kv_size, ns] semantics regardless of stream
count.
performance reasons.
…nto deepseek_v3_2_exp
remove any score-shaping bias (e.g., ALiBi) from that step. Apply ALiBi only in the final attention computation.
tilelang implementations.
compute_indexer_triplet: lower epsilon in K-indexer normalization
by ensuring dStarts and dEnds are populated.
itself, compiled to cuda c. Note that this creates a dependency on cutlass, so this may forever stay on my private branch.
unit test is failing. Working on it.
fp8 in cuda too. Still not working though.
src/llama-sparse-indexer.cpp where it belongs.
idx_compute_scores_tile ) with the k_indexer_logits_tiled_f32 kernel. In the process, identified and fixed two bugs in idx_compute_scores_tile. Next step is to hopefully use this new test as a pattern to properly unit test the tilelang kernel.
that our FP8 CPU code is correct.
**File:** `ggml/src/ggml-fp8.cpp` **Function:** `template<int E> inline float fp8_to_float(const FP8<E>& in)` Problem: For E4M3 (E=4), GGML’s generic decoder treated all 7 value bits as a finite encoding, so codes `0x7f` and `0xff` decoded to `+4 80` and `-480` instead of NaN. CUTLASS’s `float_e4m3_t` (and the CPU helper in `tests/fp8-e4m3-cpu.h`) interpret the pattern: - exponent = 0xF (all 4 exponent bits) - mantissa = 0x7 (all 3 mantissa bits) as **NaN**, independent of sign, i.e. for both `0x7f` and `0xff`.
GGML_CUDA_DISABLE_GRAPHS=1 \ LLAMA_SPARSE_PROF=1 \ LLAMA_SPARSE_PROF_EACH=1 \ LLAMA_INDEXER_TL_FP8_DEBUG=1 \ LLAMA_INDEXER_TL_PORT=1 \ LLAMA_TL_FP8=1 \ ./scripts/debug-test.sh test-indexer-fused-op-cuda 0 passes. This compares the tilelang vendored kernel with out CPU reference kernel, `idx_compute_scores_tile`.
tilelang vendored kernel mathematically. Slightly slower. 4.82 tok/s vs 6.0 tok/s on my hardware.
restores a fair bit (if not all) of the lost performance: - The inner-most `d` loop does only `dot += qv[d] * kvp[d];` - All FP8 work has been hoisted into the Qq/Kh precomputation loops, which are O(D * H * Tc + D * kv) instead of O(D * H * Tc * kv).
…nternally and matches the CPU FP8 reference, so the H=4 WMMA path test passes
… in the optimized path) now: - Uses FP8 E4M3 quantization for Q and K, - Uses the same per-row K scale `K_sf = amax/448` as the CPU reference, - Uses `k_scale * K_sf` as the final scaling, and - Matches the CPU `idx_compute_scores_tile` FP8 Lightning Indexer to ~3e-6 for the test shape.
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Don't merge. WIP.