SPI Engine: update test for SDO idle state control (#115)

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>

Author: LBFFilho

common/sv/adi_regmap_spi_engine_pkg.sv

@@ -33,7 +33,7 @@
 // ***************************************************************************
 // ***************************************************************************
 /* Auto generated Register Map */
-/* Tue Jun 25 17:14:36 2024 */
+/* Wed Jul 24 09:28:37 2024 */
 
 package adi_regmap_spi_engine_pkg;
   import adi_regmap_pkg::*;
@@ -43,8 +43,8 @@ package adi_regmap_spi_engine_pkg;
 
   const reg_t AXI_SPI_ENGINE_VERSION = '{ 'h0000, "VERSION" , '{
     "VERSION_MAJOR": '{ 31, 16, RO, 'h00000001 },
-    "VERSION_MINOR": '{ 15, 8, RO, 'h00000002 },
-    "VERSION_PATCH": '{ 7, 0, RO, 'h00000001 }}};
+    "VERSION_MINOR": '{ 15, 8, RO, 'h00000003 },
+    "VERSION_PATCH": '{ 7, 0, RO, 'h00000000 }}};
   `define SET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) SetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
   `define GET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) GetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
   `define DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR GetResetValue(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR")

common/sv/spi_engine_instr_pkg.sv

@@ -12,7 +12,7 @@ package spi_engine_instr_pkg;
 `define INST_WRD        (32'h0000_0300 | (`NUM_OF_WORDS-1))
 
 // Configuration register instructions
-`define INST_CFG        (32'h0000_2100 | (`THREE_WIRE << 2) | (`CPOL << 1) | `CPHA)
+`define INST_CFG        (32'h0000_2100 | (`SDO_IDLE_STATE << 3) | (`THREE_WIRE << 2) | (`CPOL << 1) | `CPHA)
 `define INST_PRESCALE   (32'h0000_2000 | `CLOCK_DIVIDER)
 `define INST_DLENGTH    (32'h0000_2200 | `DATA_DLENGTH)
 

spi_engine/cfgs/cfg1.tcl

@@ -20,6 +20,7 @@ set ad_project_params(DATA_DLENGTH)         18
 set ad_project_params(THREE_WIRE)           0
 set ad_project_params(CPOL)                 0
 set ad_project_params(CPHA)                 1
+set ad_project_params(SDO_IDLE_STATE)       0
 set ad_project_params(SLAVE_TIN)            0
 set ad_project_params(SLAVE_TOUT)           0
 set ad_project_params(MASTER_TIN)           0

spi_engine/cfgs/cfg_inv_cs.tcl

@@ -20,6 +20,7 @@ set ad_project_params(DATA_DLENGTH)         18
 set ad_project_params(THREE_WIRE)           0
 set ad_project_params(CPOL)                 0
 set ad_project_params(CPHA)                 1
+set ad_project_params(SDO_IDLE_STATE)       0
 set ad_project_params(SLAVE_TIN)            0
 set ad_project_params(SLAVE_TOUT)           0
 set ad_project_params(MASTER_TIN)           0

spi_engine/tests/test_program.sv

@@ -52,7 +52,7 @@ import adi_spi_vip_pkg::*;
 //---------------------------------------------------------------------------
 // SPI Engine configuration parameters
 //---------------------------------------------------------------------------
-localparam PCORE_VERSION              = 32'h0001_0201;
+localparam PCORE_VERSION              = 32'h0001_0300;
 
 program test_program (
   inout spi_engine_irq,
@@ -339,7 +339,7 @@ task fifo_spi_test();
   #100ns
   // Generate a FIFO transaction, write SDO first
   repeat (`NUM_OF_WORDS) begin
-    axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (16'hDEAD << (`DATA_WIDTH - `DATA_DLENGTH)));
+    axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (16'hDEAC ));
   end
 
   // Enqueue transfer to DUT

spi_engine/tests/test_sleep_delay.sv

@@ -50,7 +50,7 @@ import adi_spi_vip_pkg::*;
 //---------------------------------------------------------------------------
 // SPI Engine configuration parameters
 //---------------------------------------------------------------------------
-localparam PCORE_VERSION              = 32'h0001_0201;
+localparam PCORE_VERSION              = 32'h0001_0300;
 
 program test_sleep_delay (
   inout spi_engine_irq,