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AD738x testbench (#113)
ad738x_testbench Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
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‎ad738x/Makefile‎

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####################################################################################
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####################################################################################
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## Copyright 2021(c) Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# All test-bench dependencies except test programs
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SV_DEPS += ../common/sv/utils.svh
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SV_DEPS += ../common/sv/logger_pkg.sv
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SV_DEPS += ../common/sv/reg_accessor.sv
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SV_DEPS += ../common/sv/m_axis_sequencer.sv
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SV_DEPS += ../common/sv/s_axis_sequencer.sv
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SV_DEPS += ../common/sv/m_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_axi_sequencer.sv
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SV_DEPS += ../common/sv/dmac_api.sv
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SV_DEPS += ../common/sv/adi_regmap_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_clkgen_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_spi_engine_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_pwm_gen_pkg.sv
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SV_DEPS += ../common/sv/dma_trans.sv
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SV_DEPS += system_tb.sv
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ENV_DEPS += system_project.tcl
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ENV_DEPS += system_bd.tcl
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ENV_DEPS +=../scripts/adi_sim.tcl
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ENV_DEPS +=../scripts/run_sim.tcl
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_sysid
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LIB_DEPS += spi_engine/axi_spi_engine
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LIB_DEPS += spi_engine/spi_engine_execution
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LIB_DEPS += spi_engine/spi_engine_interconnect
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LIB_DEPS += spi_engine/spi_engine_offload
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_axis_upscale
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LIB_DEPS += util_pulse_gen
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# default test programs
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# Format is: <test name>
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TP := $(notdir $(basename $(wildcard tests/*.sv)))
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP)))
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include ../scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=cfg1 TST=test_program MODE=gui
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#
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# run all test from a configuration
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# make cfg1
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####################################################################################
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####################################################################################

‎ad738x/README.md‎

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension

‎ad738x/cfgs/cfg1.tcl‎

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global ad_project_params
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set ad_project_params(ALERT_SPI_N) 0
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set ad_project_params(NUM_OF_SDI) 2

‎ad738x/system_bd.tcl‎

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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../../scripts/adi_env.tcl
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# system level parameters
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global ad_project_params
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#
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# Block design under test
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#
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source ../../projects/ad738x_fmc/common/ad738x_bd.tcl
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create_bd_port -dir O ad738x_spi_clk
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create_bd_port -dir O ad738x_irq
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ad_connect ad738x_spi_clk spi_clkgen/clk_0
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ad_connect ad738x_irq spi_ad738x_adc/irq
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set BA_SPI_REGMAP 0x44A00000
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set_property offset $BA_SPI_REGMAP [get_bd_addr_segs {mng_axi_vip/Master_AXI/spi_ad738x_adc_axi_regmap}]
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adi_sim_add_define "SPI_AD738x_REGMAP_BA=[format "%d" ${BA_SPI_REGMAP}]"
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set BA_DMA 0x44A30000
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set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad738x_dma}]
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adi_sim_add_define "AD738x_DMA_BA=[format "%d" ${BA_DMA}]"
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set BA_PWM 0x44B00000
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set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_trigger_gen}]
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adi_sim_add_define "AD738x_PWM_GEN_BA=[format "%d" ${BA_PWM}]"
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set BA_CLKGEN 0x44A70000
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set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_clkgen}]
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adi_sim_add_define "AD738x_AXI_CLKGEN_BA=[format "%d" ${BA_CLKGEN}]"

‎ad738x/system_project.tcl‎

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source ../scripts/adi_sim.tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read common config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Set project params
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#global ad_project_params
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#set SER_PAR_N $ad_project_params(SER_PAR_N)
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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#global mng_axi_cfg
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global use_smartconnect
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if {[expr {![info exists use_smartconnect]}]} {
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set use_smartconnect 1
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}
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# Create the project
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adi_sim_project_xilinx $project_name "xc7z007sclg400-1"
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# Add test files to the project
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adi_sim_project_files [list \
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"../common/sv/utils.svh" \
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"../common/sv/logger_pkg.sv" \
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"../common/sv/reg_accessor.sv" \
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"../common/sv/m_axis_sequencer.sv" \
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"../common/sv/s_axis_sequencer.sv" \
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"../common/sv/m_axi_sequencer.sv" \
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"../common/sv/s_axi_sequencer.sv" \
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"../common/sv/dmac_api.sv" \
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"../common/sv/adi_regmap_pkg.sv" \
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"../common/sv/adi_regmap_clkgen_pkg.sv" \
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"../common/sv/adi_regmap_dmac_pkg.sv" \
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"../common/sv/adi_regmap_spi_engine_pkg.sv" \
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"../common/sv/adi_regmap_pwm_gen_pkg.sv" \
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"../common/sv/dma_trans.sv" \
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"../common/sv/test_harness_env.sv" \
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"tests/test_program.sv" \
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"system_tb.sv"]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

‎ad738x/system_tb.sv‎

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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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`include "utils.svh"
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module system_tb();
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wire ad738x_spi_sclk;
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wire ad738x_spi_sdo;
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wire [`NUM_OF_SDI-1:0] ad738x_spi_sdi;
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wire ad738x_spi_cs;
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wire ad738x_spi_clk;
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wire ad738x_irq;
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`TEST_PROGRAM test(
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.ad738x_spi_clk (ad738x_spi_clk),
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.ad738x_irq (ad738x_irq),
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.ad738x_spi_sdi(ad738x_spi_sdi),
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.ad738x_spi_cs (ad738x_spi_cs),
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.ad738x_spi_sclk (ad738x_spi_sclk));
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test_harness `TH (
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.ad738x_spi_clk (ad738x_spi_clk),
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.irq (),
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.ad738x_irq(ad738x_irq),
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.ad738x_spi_sdo (ad738x_spi_sdo),
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.ad738x_spi_sdi (ad738x_spi_sdi),
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.ad738x_spi_cs (ad738x_spi_cs),
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.ad738x_spi_sclk (ad738x_spi_sclk));
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endmodule

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