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pluto: Add testbench for Pluto
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
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‎pluto/Makefile‎

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####################################################################################
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## Copyright (C) 2024 Analog Devices, Inc.
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####################################################################################
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# All test-bench dependencies except test programs
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SV_DEPS += ../common/sv/utils.svh
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SV_DEPS += ../common/sv/logger_pkg.sv
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SV_DEPS += ../common/sv/reg_accessor.sv
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SV_DEPS += ../common/sv/m_axis_sequencer.sv
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SV_DEPS += ../common/sv/s_axis_sequencer.sv
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SV_DEPS += ../common/sv/m_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_axi_sequencer.sv
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SV_DEPS += ../common/sv/adi_regmap_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_dac_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_adc_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_common_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_tdd_gen_pkg.sv
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SV_DEPS += ../common/sv/dmac_api.sv
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SV_DEPS += ../common/sv/dma_trans.sv
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SV_DEPS += ../common/sv/test_harness_env.sv
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SV_DEPS += system_tb.sv
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ENV_DEPS += system_project.tcl
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ENV_DEPS += system_bd.tcl
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ENV_DEPS +=../scripts/adi_sim.tcl
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ENV_DEPS +=../scripts/run_sim.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_tdd
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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# default test program
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TP := test_program
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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#$(warning $(CFG_FILES))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
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#TESTS += cfg1_mm2mm_default:directed_test
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#TESTS += cfg1:test_program
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#TESTS += cfg2_fsync:test_program
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#TESTS += cfg2_fsync:test_frame_delay
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include ../scripts/project-sim.mk

‎pluto/README.md‎

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎pluto/cfgs/cfg1.tcl‎

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global ad_project_params
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# Put project configs here
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# e.g.
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# set ad_project_params(CMOS_LVDS_N) 1
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‎pluto/system_bd.tcl‎

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# ***************************************************************************
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# ***************************************************************************
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# Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../../scripts/adi_env.tcl
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global ad_project_params
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# Device clk
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ad_ip_instance clk_vip ssi_clk_vip [ list \
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INTERFACE_MODE {MASTER} \
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FREQ_HZ 250000000 \
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]
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adi_sim_add_define "SSI_CLK=ssi_clk_vip"
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create_bd_port -dir O ssi_clk_out
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ad_connect ssi_clk_out ssi_clk_vip/clk_out
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# Remove duplicated objects
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delete_bd_objs \
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[get_bd_cells sys_concat_intc] \
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[get_bd_cells sys_rstgen]
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ad_disconnect [get_bd_pins sys_clk_vip/clk_out] sys_cpu_clk
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# Block design under test
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source $ad_hdl_dir/projects/pluto/system_bd.tcl
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# Remove unnecessary objects
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delete_bd_objs \
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[get_bd_intf_nets axi_ad9361_adc_dma_m_dest_axi] \
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[get_bd_intf_nets axi_ad9361_dac_dma_m_src_axi] \
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[get_bd_intf_nets S00_AXI_1] \
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[get_bd_intf_nets sys_ps7_DDR] \
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[get_bd_intf_nets sys_ps7_FIXED_IO] \
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[get_bd_nets gpio_i_1] \
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[get_bd_nets spi0_clk_i_1] \
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[get_bd_nets spi0_csn_i_1] \
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[get_bd_nets spi0_sdi_i_1] \
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[get_bd_nets spi0_sdo_i_1] \
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[get_bd_nets sys_200m_clk] \
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[get_bd_nets sys_concat_intc_dout] \
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[get_bd_nets sys_ps7_FCLK_RESET0_N] \
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[get_bd_nets sys_ps7_GPIO_O] \
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[get_bd_nets sys_ps7_GPIO_T] \
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[get_bd_nets sys_ps7_SPI0_MOSI_O] \
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[get_bd_nets sys_ps7_SPI0_SCLK_O] \
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[get_bd_nets sys_ps7_SPI0_SS_O] \
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[get_bd_nets sys_ps7_SPI0_SS1_O] \
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[get_bd_nets sys_ps7_SPI0_SS2_O] \
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[get_bd_cells sys_ps7]
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ad_connect sys_cpu_clk sys_clk_vip/clk_out
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ad_connect sys_cpu_clk mng_axi_vip/aclk
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ad_connect sys_cpu_clk axi_intc/s_axi_aclk
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ad_connect sys_cpu_clk axi_axi_interconnect/aclk
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ad_connect sys_cpu_clk axi_mem_interconnect/aclk1
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ad_connect sys_rst_vip/rst_out sys_rstgen/ext_reset_in
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ad_connect axi_intc/intr sys_concat_intc/dout
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ad_connect $sys_iodelay_clk axi_ad9361/delay_clk
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
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ad_ip_parameter axi_ad9361 CONFIG.DELAY_REFCLK_FREQUENCY 400
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set RX_DMA 0x7C400000
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set_property offset $RX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9361_adc_dma}]
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adi_sim_add_define "RX_DMA_BA=[format "%d" ${RX_DMA}]"
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set TX_DMA 0x7C420000
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set_property offset $TX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9361_dac_dma}]
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adi_sim_add_define "TX_DMA_BA=[format "%d" ${TX_DMA}]"
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set TDDN 0x7C440000
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set_property offset $TDDN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_tdd_0}]
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adi_sim_add_define "TDDN_BA=[format "%d" ${TDDN}]"
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set AXI_AD9361 0x79020000
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set_property offset $AXI_AD9361 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad9361}]
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adi_sim_add_define "AXI_AD9361_BA=[format "%d" ${AXI_AD9361}]"

‎pluto/system_project.tcl‎

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source ../scripts/adi_sim.tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read common config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Create the project
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adi_sim_project_xilinx $project_name "xc7z010clg400-1"
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# Add test files to the project
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adi_sim_project_files [list \
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"../common/sv/utils.svh" \
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"../common/sv/logger_pkg.sv" \
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"../common/sv/reg_accessor.sv" \
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"../common/sv/m_axis_sequencer.sv" \
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"../common/sv/s_axis_sequencer.sv" \
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"../common/sv/m_axi_sequencer.sv" \
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"../common/sv/s_axi_sequencer.sv" \
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"../common/sv/adi_regmap_pkg.sv" \
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"../common/sv/adi_regmap_dmac_pkg.sv" \
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"../common/sv/adi_regmap_dac_pkg.sv" \
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"../common/sv/adi_regmap_adc_pkg.sv" \
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"../common/sv/adi_regmap_common_pkg.sv" \
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"../common/sv/adi_regmap_tdd_gen_pkg.sv" \
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"../common/sv/dmac_api.sv" \
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"../common/sv/dma_trans.sv" \
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"../common/sv/test_harness_env.sv" \
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"tests/test_program.sv" \
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"system_tb.sv" \
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]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

‎pluto/system_tb.sv‎

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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`include "utils.svh"
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module system_tb();
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logic burst = 1'b0;
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logic txdata;
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logic [11:0] tx_data_out;
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`TEST_PROGRAM test();
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test_harness `TH (
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.ssi_clk_out (ssi_clk),
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.enable (enable),
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.rx_clk_in (rx_clk_in),
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.rx_data_in (tx_data_out),
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.rx_frame_in (tx_frame_out),
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.tx_clk_out (tx_clk_out),
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.tx_data_out (tx_data_out),
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.tx_frame_out (tx_frame_out),
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.txnrx (txnrx),
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.up_enable (1'b1),
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.up_txnrx (1'b1),
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.tdd_ext_sync(burst),
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.txdata_o(txdata)
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);
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assign rx_clk_in = ssi_clk;
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endmodule

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