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adrv9009: Update the testbench configuration
The configuration files were updated to emulate the zcu102 use cases. This commit also addresses the issue in which the SmartConnect emulating the CPU will generate an error if it has more than 16 interfaces connected to it by using an Interconnect instead of SmartConnect. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
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13 files changed

+119
-205
lines changed

13 files changed

+119
-205
lines changed

‎adrv9009/cfgs/cfg1.tcl‎

100755100644
Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,29 @@
1-
global ad_project_params
2-
3-
set ad_project_params(LINK_MODE) 1
4-
5-
set ad_project_params(REF_CLK_RATE) 500
6-
set ad_project_params(LANE_RATE) 10
7-
8-
set ad_project_params(DAC_FIFO_ADDRESS_WIDTH) 16
9-
10-
set ad_project_params(TX_JESD_M) 1
11-
set ad_project_params(TX_JESD_L) 1
12-
set ad_project_params(TX_JESD_S) 1
13-
set ad_project_params(TX_JESD_NP) 16
14-
set ad_project_params(TX_JESD_F) 2
15-
set ad_project_params(TX_JESD_K) 32
16-
17-
set ad_project_params(RX_JESD_M) 1
18-
set ad_project_params(RX_JESD_L) 1
19-
set ad_project_params(RX_JESD_S) 1
20-
set ad_project_params(RX_JESD_NP) 16
21-
set ad_project_params(RX_JESD_F) 2
22-
set ad_project_params(RX_JESD_K) 32
23-
24-
set ad_project_params(RX_OS_JESD_M) 1
25-
set ad_project_params(RX_OS_JESD_L) 1
26-
set ad_project_params(RX_OS_JESD_S) 2
27-
set ad_project_params(RX_OS_JESD_NP) 16
28-
set ad_project_params(RX_OS_JESD_F) 4
29-
set ad_project_params(RX_OS_JESD_K) 32
1+
global ad_project_params
2+
3+
set ad_project_params(LINK_MODE) 1
4+
5+
set ad_project_params(REF_CLK_RATE) 500
6+
set ad_project_params(LANE_RATE) 10
7+
8+
set ad_project_params(DAC_FIFO_ADDRESS_WIDTH) 16
9+
10+
set ad_project_params(TX_JESD_M) 2
11+
set ad_project_params(TX_JESD_L) 1
12+
set ad_project_params(TX_JESD_S) 1
13+
set ad_project_params(TX_JESD_NP) 16
14+
set ad_project_params(TX_JESD_F) 4
15+
set ad_project_params(TX_JESD_K) 32
16+
17+
set ad_project_params(RX_JESD_M) 4
18+
set ad_project_params(RX_JESD_L) 1
19+
set ad_project_params(RX_JESD_S) 1
20+
set ad_project_params(RX_JESD_NP) 16
21+
set ad_project_params(RX_JESD_F) 8
22+
set ad_project_params(RX_JESD_K) 32
23+
24+
set ad_project_params(RX_OS_JESD_M) 2
25+
set ad_project_params(RX_OS_JESD_L) 1
26+
set ad_project_params(RX_OS_JESD_S) 1
27+
set ad_project_params(RX_OS_JESD_NP) 16
28+
set ad_project_params(RX_OS_JESD_F) 4
29+
set ad_project_params(RX_OS_JESD_K) 32

‎adrv9009/cfgs/cfg2.tcl‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -7,23 +7,23 @@ set ad_project_params(LANE_RATE) 10
77

88
set ad_project_params(DAC_FIFO_ADDRESS_WIDTH) 16
99

10-
set ad_project_params(TX_JESD_M) 1
10+
set ad_project_params(TX_JESD_M) 2
1111
set ad_project_params(TX_JESD_L) 2
1212
set ad_project_params(TX_JESD_S) 1
1313
set ad_project_params(TX_JESD_NP) 16
14-
set ad_project_params(TX_JESD_F) 1
14+
set ad_project_params(TX_JESD_F) 2
1515
set ad_project_params(TX_JESD_K) 32
1616

17-
set ad_project_params(RX_JESD_M) 1
18-
set ad_project_params(RX_JESD_L) 2
17+
set ad_project_params(RX_JESD_M) 4
18+
set ad_project_params(RX_JESD_L) 1
1919
set ad_project_params(RX_JESD_S) 1
2020
set ad_project_params(RX_JESD_NP) 16
21-
set ad_project_params(RX_JESD_F) 1
21+
set ad_project_params(RX_JESD_F) 8
2222
set ad_project_params(RX_JESD_K) 32
2323

24-
set ad_project_params(RX_OS_JESD_M) 1
25-
set ad_project_params(RX_OS_JESD_L) 2
26-
set ad_project_params(RX_OS_JESD_S) 2
24+
set ad_project_params(RX_OS_JESD_M) 2
25+
set ad_project_params(RX_OS_JESD_L) 1
26+
set ad_project_params(RX_OS_JESD_S) 1
2727
set ad_project_params(RX_OS_JESD_NP) 16
28-
set ad_project_params(RX_OS_JESD_F) 2
28+
set ad_project_params(RX_OS_JESD_F) 4
2929
set ad_project_params(RX_OS_JESD_K) 32

‎adrv9009/cfgs/cfg3.tcl‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,23 +7,23 @@ set ad_project_params(LANE_RATE) 10
77

88
set ad_project_params(DAC_FIFO_ADDRESS_WIDTH) 16
99

10-
set ad_project_params(TX_JESD_M) 1
10+
set ad_project_params(TX_JESD_M) 4
1111
set ad_project_params(TX_JESD_L) 2
1212
set ad_project_params(TX_JESD_S) 1
1313
set ad_project_params(TX_JESD_NP) 16
14-
set ad_project_params(TX_JESD_F) 1
14+
set ad_project_params(TX_JESD_F) 4
1515
set ad_project_params(TX_JESD_K) 32
1616

17-
set ad_project_params(RX_JESD_M) 1
17+
set ad_project_params(RX_JESD_M) 4
1818
set ad_project_params(RX_JESD_L) 2
19-
set ad_project_params(RX_JESD_S) 4
19+
set ad_project_params(RX_JESD_S) 1
2020
set ad_project_params(RX_JESD_NP) 16
2121
set ad_project_params(RX_JESD_F) 4
2222
set ad_project_params(RX_JESD_K) 32
2323

24-
set ad_project_params(RX_OS_JESD_M) 1
24+
set ad_project_params(RX_OS_JESD_M) 4
2525
set ad_project_params(RX_OS_JESD_L) 2
26-
set ad_project_params(RX_OS_JESD_S) 4
26+
set ad_project_params(RX_OS_JESD_S) 1
2727
set ad_project_params(RX_OS_JESD_NP) 16
2828
set ad_project_params(RX_OS_JESD_F) 4
2929
set ad_project_params(RX_OS_JESD_K) 32

‎adrv9009/cfgs/cfg4.tcl‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -7,23 +7,23 @@ set ad_project_params(LANE_RATE) 10
77

88
set ad_project_params(DAC_FIFO_ADDRESS_WIDTH) 16
99

10-
set ad_project_params(TX_JESD_M) 2
11-
set ad_project_params(TX_JESD_L) 1
10+
set ad_project_params(TX_JESD_M) 4
11+
set ad_project_params(TX_JESD_L) 4
1212
set ad_project_params(TX_JESD_S) 1
1313
set ad_project_params(TX_JESD_NP) 16
14-
set ad_project_params(TX_JESD_F) 4
14+
set ad_project_params(TX_JESD_F) 2
1515
set ad_project_params(TX_JESD_K) 32
1616

17-
set ad_project_params(RX_JESD_M) 2
18-
set ad_project_params(RX_JESD_L) 1
17+
set ad_project_params(RX_JESD_M) 4
18+
set ad_project_params(RX_JESD_L) 2
1919
set ad_project_params(RX_JESD_S) 1
2020
set ad_project_params(RX_JESD_NP) 16
2121
set ad_project_params(RX_JESD_F) 4
2222
set ad_project_params(RX_JESD_K) 32
2323

2424
set ad_project_params(RX_OS_JESD_M) 2
25-
set ad_project_params(RX_OS_JESD_L) 1
25+
set ad_project_params(RX_OS_JESD_L) 2
2626
set ad_project_params(RX_OS_JESD_S) 1
2727
set ad_project_params(RX_OS_JESD_NP) 16
28-
set ad_project_params(RX_OS_JESD_F) 4
28+
set ad_project_params(RX_OS_JESD_F) 2
2929
set ad_project_params(RX_OS_JESD_K) 32

‎adrv9009/cfgs/cfg5.tcl‎

Lines changed: 0 additions & 29 deletions
This file was deleted.

‎adrv9009/cfgs/cfg6.tcl‎

Lines changed: 0 additions & 29 deletions
This file was deleted.

‎adrv9009/cfgs/cfg7.tcl‎

Lines changed: 0 additions & 29 deletions
This file was deleted.

‎adrv9009/cfgs/cfg8.tcl‎

Lines changed: 0 additions & 29 deletions
This file was deleted.

‎adrv9009/system_bd.tcl‎

Lines changed: 30 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# ***************************************************************************
22
# ***************************************************************************
3-
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
3+
# Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
44
#
55
# In this HDL repository, there are many different and unique modules, consisting
66
# of various HDL (Verilog or VHDL) components. The individual modules are
@@ -140,6 +140,15 @@ adi_sim_add_define "TX_DEVICE_CLK=tx_device_clk_vip"
140140
create_bd_port -dir O tx_device_clk_out
141141
ad_connect tx_device_clk_out tx_device_clk_vip/clk_out
142142

143+
# Tx Link clk
144+
ad_ip_instance clk_vip tx_link_clk_vip [ list \
145+
INTERFACE_MODE {MASTER} \
146+
FREQ_HZ 250000000 \
147+
]
148+
adi_sim_add_define "TX_LINK_CLK=tx_link_clk_vip"
149+
create_bd_port -dir O tx_link_clk_out
150+
ad_connect tx_link_clk_out tx_link_clk_vip/clk_out
151+
143152
# Tx Observation Device clk
144153
ad_ip_instance clk_vip tx_os_device_clk_vip [ list \
145154
INTERFACE_MODE {MASTER} \
@@ -165,11 +174,13 @@ ad_connect sysref_clk_out sysref_clk_vip/clk_out
165174
create_bd_port -dir I -type clk ref_clk_ex
166175
create_bd_port -dir I -type clk rx_device_clk
167176
create_bd_port -dir I -type clk tx_device_clk
177+
create_bd_port -dir I -type clk tx_link_clk
168178
create_bd_port -dir I -type clk tx_os_device_clk
169179
create_bd_port -dir I -type clk sysref
170180

171181
set_property CONFIG.FREQ_HZ 250000000 [get_bd_ports rx_device_clk]
172182
set_property CONFIG.FREQ_HZ 250000000 [get_bd_ports tx_device_clk]
183+
set_property CONFIG.FREQ_HZ 250000000 [get_bd_ports tx_link_clk]
173184
set_property CONFIG.FREQ_HZ 250000000 [get_bd_ports tx_os_device_clk]
174185

175186
for {set i 0} {$i < $TX_MAX_LANES} {incr i} {
@@ -214,20 +225,23 @@ create_bd_cell -type container -reference tx_os_jesd_exerciser i_tx_os_jesd_exer
214225

215226
# Rx exerciser
216227
for {set i 0} {$i < $TX_NUM_OF_LANES} {incr i} {
217-
ad_connect rx_data1_${i}_n i_rx_jesd_exerciser/rx_data_${i}_n
218-
ad_connect rx_data1_${i}_p i_rx_jesd_exerciser/rx_data_${i}_p
228+
set j [expr {$TX_NUM_OF_LANES == 2} ? $i*2 : $i]
229+
ad_connect rx_data1_${j}_n i_rx_jesd_exerciser/rx_data_${i}_n
230+
ad_connect rx_data1_${j}_p i_rx_jesd_exerciser/rx_data_${i}_p
219231
}
220232
ad_connect sysref i_rx_jesd_exerciser/rx_sysref_0
221233

222234
ad_connect $sys_cpu_clk i_rx_jesd_exerciser/sys_cpu_clk
223235
ad_connect $sys_cpu_resetn i_rx_jesd_exerciser/sys_cpu_resetn
224236

225237
ad_connect rx_device_clk i_rx_jesd_exerciser/device_clk
226-
238+
ad_connect rx_device_clk i_rx_jesd_exerciser/link_clk
227239
ad_connect ref_clk_ex i_rx_jesd_exerciser/ref_clk
228240

229-
set_property -dict [list CONFIG.NUM_MI {18}] [get_bd_cells axi_cpu_interconnect]
230-
ad_connect i_rx_jesd_exerciser/S00_AXI_0 axi_cpu_interconnect/M17_AXI
241+
set_property -dict [list CONFIG.NUM_MI {18}] [get_bd_cells axi_axi_interconnect]
242+
ad_connect i_rx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M17_AXI
243+
ad_connect sys_cpu_clk axi_axi_interconnect/M17_ACLK
244+
ad_connect sys_cpu_resetn axi_axi_interconnect/M17_ARESETN
231245

232246
create_bd_port -dir O ex_rx_sync
233247
ad_connect ex_rx_sync i_rx_jesd_exerciser/rx_sync_0
@@ -243,11 +257,13 @@ ad_connect $sys_cpu_clk i_tx_jesd_exerciser/sys_cpu_clk
243257
ad_connect $sys_cpu_resetn i_tx_jesd_exerciser/sys_cpu_resetn
244258

245259
ad_connect tx_device_clk i_tx_jesd_exerciser/device_clk
246-
260+
ad_connect tx_link_clk i_tx_jesd_exerciser/link_clk
247261
ad_connect ref_clk_ex i_tx_jesd_exerciser/ref_clk
248262

249-
set_property -dict [list CONFIG.NUM_MI {19}] [get_bd_cells axi_cpu_interconnect]
250-
ad_connect i_tx_jesd_exerciser/S00_AXI_0 axi_cpu_interconnect/M18_AXI
263+
set_property -dict [list CONFIG.NUM_MI {19}] [get_bd_cells axi_axi_interconnect]
264+
ad_connect i_tx_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M18_AXI
265+
ad_connect sys_cpu_clk axi_axi_interconnect/M18_ACLK
266+
ad_connect sys_cpu_resetn axi_axi_interconnect/M18_ARESETN
251267

252268
create_bd_port -dir I ex_tx_sync
253269
ad_connect ex_tx_sync i_tx_jesd_exerciser/tx_sync_0
@@ -272,11 +288,13 @@ ad_connect $sys_cpu_clk i_tx_os_jesd_exerciser/sys_cpu_clk
272288
ad_connect $sys_cpu_resetn i_tx_os_jesd_exerciser/sys_cpu_resetn
273289

274290
ad_connect tx_os_device_clk i_tx_os_jesd_exerciser/device_clk
275-
291+
ad_connect tx_os_device_clk i_tx_os_jesd_exerciser/link_clk
276292
ad_connect ref_clk_ex i_tx_os_jesd_exerciser/ref_clk
277293

278-
set_property -dict [list CONFIG.NUM_MI {20}] [get_bd_cells axi_cpu_interconnect]
279-
ad_connect i_tx_os_jesd_exerciser/S00_AXI_0 axi_cpu_interconnect/M19_AXI
294+
set_property -dict [list CONFIG.NUM_MI {20}] [get_bd_cells axi_axi_interconnect]
295+
ad_connect i_tx_os_jesd_exerciser/S00_AXI_0 axi_axi_interconnect/M19_AXI
296+
ad_connect sys_cpu_clk axi_axi_interconnect/M19_ACLK
297+
ad_connect sys_cpu_resetn axi_axi_interconnect/M19_ARESETN
280298

281299
create_bd_port -dir I ex_tx_os_sync
282300
ad_connect ex_tx_os_sync i_tx_os_jesd_exerciser/tx_sync_0

‎adrv9009/system_project.tcl‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,9 @@ source "cfgs/${cfg_file}"
1515
# Set the project name
1616
set project_name [file rootname $cfg_file]
1717

18+
# Set to use SmartConnect or AXI Interconnect
19+
set use_smartconnect 0
20+
1821
# Create the project
1922
#adi_sim_project_xilinx $project_name "xcvm1802-vfvc1760-3HP-e-S"
2023
adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"

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