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IstvanZsSzekelyIstvanZsSzekely
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library/vip/amd/axi/s_axi_sequencer: Added memory access functions
- Updated testbenches as well Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
1 parent a6483d7 commit a8c9d2d

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28 files changed

+111
-164
lines changed

28 files changed

+111
-164
lines changed

‎library/vip/amd/axi/s_axi_sequencer.sv‎

Lines changed: 16 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -52,26 +52,14 @@ package s_axi_sequencer_pkg;
5252
super.new(name, parent);
5353
endfunction: new
5454

55-
virtual task get_byte_from_mem(
56-
input xil_axi_ulong addr,
57-
output bit [7:0] data);
58-
59-
this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
60-
endtask: get_byte_from_mem
55+
virtual function logic [31:0] get_reg_data_from_mem(input xil_axi_ulong addr);
56+
endfunction: get_reg_data_from_mem
6157

62-
virtual task set_byte_in_mem(
58+
virtual function void set_reg_data_in_mem(
6359
input xil_axi_ulong addr,
64-
input bit [7:0] data);
65-
66-
this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
67-
endtask: set_byte_in_mem
68-
69-
virtual task verify_byte(
70-
input xil_axi_ulong addr,
71-
input bit [7:0] refdata);
72-
73-
this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));
74-
endtask: verify_byte
60+
input logic [31:0] data,
61+
input bit [3:0] strb);
62+
endfunction: set_reg_data_in_mem
7563

7664
endclass: s_axi_sequencer_base
7765

@@ -90,47 +78,19 @@ package s_axi_sequencer_pkg;
9078
this.mem_model = mem_model;
9179
endfunction: new
9280

93-
task get_byte_from_mem(
94-
input xil_axi_ulong addr,
95-
output bit [7:0] data);
96-
97-
bit [31:0] four_bytes;
98-
four_bytes = this.mem_model.backdoor_memory_read_4byte(addr);
99-
case (addr[1:0])
100-
2'b00: data = four_bytes[0+:8];
101-
2'b01: data = four_bytes[8+:8];
102-
2'b10: data = four_bytes[16+:8];
103-
2'b11: data = four_bytes[24+:8];
104-
endcase
105-
endtask: get_byte_from_mem
106-
107-
task set_byte_in_mem(
108-
input xil_axi_ulong addr,
109-
input bit [7:0] data);
110-
111-
bit [3:0] strb;
112-
case (addr[1:0])
113-
2'b00: strb = 'b0001;
114-
2'b01: strb = 'b0010;
115-
2'b10: strb = 'b0100;
116-
2'b11: strb = 'b1000;
117-
endcase
118-
this.mem_model.backdoor_memory_write_4byte(.addr(addr),
119-
.payload({4{data}}),
120-
.strb(strb));
121-
endtask: set_byte_in_mem
81+
virtual function logic [31:0] get_reg_data_from_mem(input xil_axi_ulong addr);
82+
return this.mem_model.backdoor_memory_read_4byte(addr);
83+
endfunction: get_reg_data_from_mem
12284

123-
task verify_byte(
85+
virtual function void set_reg_data_in_mem(
12486
input xil_axi_ulong addr,
125-
input bit [7:0] refdata);
126-
127-
bit [7:0] data;
87+
input logic [31:0] data,
88+
input bit [3:0] strb);
12889

129-
get_byte_from_mem (addr, data);
130-
if (data !== refdata) begin
131-
this.error($sformatf("Unexpected value at address %0h . Expected: %0h Found: %0h", addr, refdata, data));
132-
end
133-
endtask: verify_byte
90+
this.mem_model.backdoor_memory_write_4byte(.addr(addr),
91+
.payload(data),
92+
.strb(strb));
93+
endfunction: set_reg_data_in_mem
13494

13595
endclass: s_axi_sequencer
13696

‎library/vip/amd/axis/s_axis_sequencer.sv‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -129,19 +129,6 @@ package s_axis_sequencer_pkg;
129129
this.low_time_max = low_time_max;
130130
endfunction: set_low_time_range
131131

132-
// function for verifying bytes
133-
task verify_byte(input bit [7:0] refdata);
134-
bit [7:0] data;
135-
if (byte_stream.size() == 0) begin
136-
this.error($sformatf("Byte steam empty !!!"));
137-
end else begin
138-
data = byte_stream.pop_front();
139-
if (data !== refdata) begin
140-
this.error($sformatf("Unexpected data received. Expected: %0h Found: %0h Left : %0d", refdata, data, byte_stream.size()));
141-
end
142-
end
143-
endtask: verify_byte
144-
145132
// call ready generation function
146133
virtual task start();
147134
this.fatal($sformatf("Base class was instantiated instead of the parameterized class!"));

‎testbenches/ip/data_offload/tests/test_program.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ module test_program();
245245
// Memory initialization function for a 8byte DATA_WIDTH AXI4 bus
246246
task init_mem_64(longint unsigned addr, int byte_length);
247247
for (int i=0; i<byte_length; i=i+8) begin
248-
env.ddr_agent.mem_model.backdoor_memory_write_4byte(addr + i*8, i, 255);
248+
env.ddr_slave_sequencer.set_reg_data_in_mem(addr + i*8, i, 255);
249249
end
250250
endtask
251251

‎testbenches/ip/dma_loopback/tests/test_program.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ program test_program;
9292

9393
// Init test data
9494
for (int i=0;i<2048*2 ;i=i+2) begin
95-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
95+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
9696
end
9797

9898
do_transfer(
@@ -158,8 +158,8 @@ program test_program;
158158
for (int i=0;i<length/4;i=i+4) begin
159159
current_src_address = src_addr+i;
160160
current_dest_address = dest_addr+i;
161-
captured_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_dest_address);
162-
reference_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_src_address);
161+
captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
162+
reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
163163

164164
if (captured_word !== reference_word) begin
165165
`ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

‎testbenches/ip/dma_sg/tests/test_program_1d.sv‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ program test_program_1d;
9393

9494
// Init test data with incrementing 16-bit value from 0 up to address 'h8000
9595
for (int i=0;i<'h4000;i=i+2) begin
96-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
96+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
9797
end
9898

9999
// TX BLOCK
@@ -174,18 +174,18 @@ program test_program_1d;
174174
bit [31:0] src_stride,
175175
bit [31:0] dst_stride);
176176

177-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF);
178-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF);
179-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF);
180-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF);
181-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF);
182-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF);
183-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF);
184-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF);
185-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF);
186-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF);
187-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF);
188-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF);
177+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h00, flags, 'hF);
178+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h04, id, 'hF);
179+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h08, dest_addr, 'hF);
180+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h0C, 0, 'hF);
181+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h10, src_addr, 'hF);
182+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h14, 0, 'hF);
183+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h18, next_desc_addr, 'hF);
184+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h1C, 0, 'hF);
185+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h20, y_len, 'hF);
186+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h24, x_len, 'hF);
187+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h28, src_stride, 'hF);
188+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h2C, dst_stride, 'hF);
189189

190190
endtask : write_descriptor
191191

@@ -237,8 +237,8 @@ program test_program_1d;
237237
for (int i=0;i<length;i=i+4) begin
238238
current_src_address = src_addr+i;
239239
current_dest_address = dest_addr+i;
240-
captured_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_dest_address);
241-
reference_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_src_address);
240+
captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
241+
reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
242242

243243
if (captured_word !== reference_word) begin
244244
`ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

‎testbenches/ip/dma_sg/tests/test_program_2d.sv‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -96,13 +96,13 @@ program test_program_2d;
9696

9797
// Incremental data
9898
for (int j=0;j<'h800;j=j+2) begin
99-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+offset+j*2),(((j+1+'h1000*i)) << 16) | (j+'h1000*i) ,'hF);
99+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+offset+j*2),(((j+1+'h1000*i)) << 16) | (j+'h1000*i) ,'hF);
100100
end
101101
offset = offset + 'h1000;
102102

103103
// Buffer filled with 0
104104
for (int k=0;k<'h80;k=k+1) begin
105-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+offset+k*4), 32'h0,'hF);
105+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+offset+k*4), 32'h0,'hF);
106106
end
107107
offset = offset + 'h200;
108108

@@ -168,18 +168,18 @@ program test_program_2d;
168168
bit [31:0] src_stride,
169169
bit [31:0] dst_stride);
170170

171-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF);
172-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF);
173-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF);
174-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF);
175-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF);
176-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF);
177-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF);
178-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF);
179-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF);
180-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF);
181-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF);
182-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF);
171+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h00, flags, 'hF);
172+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h04, id, 'hF);
173+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h08, dest_addr, 'hF);
174+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h0C, 0, 'hF);
175+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h10, src_addr, 'hF);
176+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h14, 0, 'hF);
177+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h18, next_desc_addr, 'hF);
178+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h1C, 0, 'hF);
179+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h20, y_len, 'hF);
180+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h24, x_len, 'hF);
181+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h28, src_stride, 'hF);
182+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h2C, dst_stride, 'hF);
183183

184184
endtask : write_descriptor
185185

@@ -231,8 +231,8 @@ program test_program_2d;
231231
for (int i=0;i<length;i=i+4) begin
232232
current_src_address = src_addr+i+(i/'h1000)*'h200;
233233
current_dest_address = dest_addr+i;
234-
captured_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_dest_address);
235-
reference_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_src_address);
234+
captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
235+
reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
236236

237237
if (captured_word !== reference_word) begin
238238
`ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

‎testbenches/ip/dma_sg/tests/test_program_tr_queue.sv‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ program test_program_tr_queue;
9393

9494
// Init test data
9595
for (int i=0;i<'h4000;i=i+2) begin
96-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
96+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF);
9797
end
9898

9999
// TX BLOCK
@@ -180,18 +180,18 @@ program test_program_tr_queue;
180180
bit [31:0] src_stride,
181181
bit [31:0] dst_stride);
182182

183-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF);
184-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF);
185-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF);
186-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF);
187-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF);
188-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF);
189-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF);
190-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF);
191-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF);
192-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF);
193-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF);
194-
base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF);
183+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h00, flags, 'hF);
184+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h04, id, 'hF);
185+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h08, dest_addr, 'hF);
186+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h0C, 0, 'hF);
187+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h10, src_addr, 'hF);
188+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h14, 0, 'hF);
189+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h18, next_desc_addr, 'hF);
190+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h1C, 0, 'hF);
191+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h20, y_len, 'hF);
192+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h24, x_len, 'hF);
193+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h28, src_stride, 'hF);
194+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(desc_addr+'h2C, dst_stride, 'hF);
195195

196196
endtask : write_descriptor
197197

@@ -255,8 +255,8 @@ program test_program_tr_queue;
255255
for (int i=0;i<length;i=i+4) begin
256256
current_src_address = src_addr+i;
257257
current_dest_address = dest_addr+i;
258-
captured_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_dest_address);
259-
reference_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_src_address);
258+
captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
259+
reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
260260

261261
if (captured_word !== reference_word) begin
262262
`ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

‎testbenches/ip/hbm/tests/test_program.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ program test_program;
8787
//
8888
// // Init test data
8989
// for (int i=0;i<2048*2 ;i=i+2) begin
90-
// base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF);
90+
// base_env.ddr.slave_sequencer.set_reg_data_in_mem(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF);
9191
// end
9292
//
9393
// do_transfer(
@@ -155,8 +155,8 @@ program test_program;
155155
// for (int i=0;i<length/4;i=i+4) begin
156156
// current_src_address = src_addr+i;
157157
// current_dest_address = dest_addr+i;
158-
// captured_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_dest_address);
159-
// reference_word = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(current_src_address);
158+
// captured_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_dest_address);
159+
// reference_word = base_env.ddr.slave_sequencer.get_reg_data_from_mem(current_src_address);
160160
//
161161
// if (captured_word !== reference_word) begin
162162
// `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_dest_address,reference_word,captured_word));

‎testbenches/ip/scoreboard/tests/test_program.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -263,8 +263,8 @@ program test_program();
263263
input int byte_length);
264264
`INFO(("Initial address: %x", addr), ADI_VERBOSITY_LOW);
265265
for (int i=0; i<byte_length; i=i+8) begin
266-
// base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(addr + i*8, i, 255);
267-
ddr.agent.mem_model.backdoor_memory_write_4byte(addr + i*8, i, 255);
266+
base_env.ddr.slave_sequencer.set_reg_data_in_mem(addr + i*8, i, 255);
267+
// ddr.slave_sequencer.set_reg_data_in_mem(addr + i*8, i, 255);
268268
end
269269
`INFO(("Final address: %x", addr + byte_length*8), ADI_VERBOSITY_LOW);
270270
endtask

‎testbenches/ip/spi_engine/tests/test_program.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,7 @@ program test_program (
357357
end
358358

359359
for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin
360-
sdi_read_data[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i));
360+
sdi_read_data[i] = base_env.ddr.slave_sequencer.get_reg_data_from_mem(xil_axi_uint'(`DDR_BA + 4*i));
361361
if (sdi_read_data[i] != sdi_read_data_store[i]) begin
362362
`INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW);
363363
`ERROR(("Offload Read Test FAILED"));

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