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IstvanZsSzekelyIstvanZsSzekely
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ADI AMD agent abstractication: Updated testbenches for the base environment
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
1 parent e87f281 commit a6483d7

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39 files changed

+1245
-926
lines changed

39 files changed

+1245
-926
lines changed

‎testbenches/ip/axi_tdd/tests/test_program.sv‎

Lines changed: 77 additions & 63 deletions
Large diffs are not rendered by default.

‎testbenches/ip/axis_sequencers/tests/test_program.sv‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737

3838
import logger_pkg::*;
3939
import test_harness_env_pkg::*;
40+
import adi_axi_agent_pkg::*;
4041
import environment_pkg::*;
4142
import watchdog_pkg::*;
4243
import axi4stream_vip_pkg::*;
@@ -52,7 +53,11 @@ import `PKGIFY(test_harness, dst_axis)::*;
5253
program test_program;
5354

5455
// declare the class instances
55-
test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env;
56+
test_harness_env base_env;
57+
58+
adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng;
59+
adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr;
60+
5661
axis_sequencer_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis), `AXIS_VIP_PARAMS(test_harness, dst_axis)) axis_seq_env;
5762

5863
watchdog send_data_wd;
@@ -61,12 +66,16 @@ program test_program;
6166

6267
// create environment
6368
base_env = new("Base Environment",
64-
`TH.`SYS_CLK.inst.IF,
65-
`TH.`DMA_CLK.inst.IF,
66-
`TH.`DDR_CLK.inst.IF,
67-
`TH.`SYS_RST.inst.IF,
68-
`TH.`MNG_AXI.inst.IF,
69-
`TH.`DDR_AXI.inst.IF);
69+
`TH.`SYS_CLK.inst.IF,
70+
`TH.`DMA_CLK.inst.IF,
71+
`TH.`DDR_CLK.inst.IF,
72+
`TH.`SYS_RST.inst.IF);
73+
74+
mng = new("", `TH.`MNG_AXI.inst.IF);
75+
ddr = new("", `TH.`DDR_AXI.inst.IF);
76+
77+
`LINK(mng, base_env, mng)
78+
`LINK(ddr, base_env, ddr)
7079

7180
axis_seq_env = new("Axis Sequencers Environment",
7281
`TH.`SRC_AXIS.inst.IF,

‎testbenches/ip/base/tests/test_program.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -66,10 +66,10 @@ program test_program;
6666

6767
// Create environment
6868
base_env = new("Base Environment",
69-
`TH.`SYS_CLK.inst.IF,
70-
`TH.`DMA_CLK.inst.IF,
71-
`TH.`DDR_CLK.inst.IF,
72-
`TH.`SYS_RST.inst.IF);
69+
`TH.`SYS_CLK.inst.IF,
70+
`TH.`DMA_CLK.inst.IF,
71+
`TH.`DDR_CLK.inst.IF,
72+
`TH.`SYS_RST.inst.IF);
7373

7474
mng = new("", `TH.`MNG_AXI.inst.IF);
7575
ddr = new("", `TH.`DDR_AXI.inst.IF);

‎testbenches/ip/dma_flock/tests/test_program.sv‎

Lines changed: 22 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
import logger_pkg::*;
3939
import environment_pkg::*;
4040
import test_harness_env_pkg::*;
41+
import adi_axi_agent_pkg::*;
4142
import axi_vip_pkg::*;
4243
import axi4stream_vip_pkg::*;
4344
import adi_regmap_pkg::*;
@@ -54,7 +55,11 @@ import `PKGIFY(test_harness, dst_axis_vip)::*;
5455
program test_program;
5556

5657
// declare the class instances
57-
test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env;
58+
test_harness_env base_env;
59+
60+
adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng;
61+
adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr;
62+
5863
dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env;
5964

6065
// Register accessors
@@ -69,12 +74,16 @@ program test_program;
6974
initial begin
7075
//creating environment
7176
base_env = new("Base Environment",
72-
`TH.`SYS_CLK.inst.IF,
73-
`TH.`DMA_CLK.inst.IF,
74-
`TH.`DDR_CLK.inst.IF,
75-
`TH.`SYS_RST.inst.IF,
76-
`TH.`MNG_AXI.inst.IF,
77-
`TH.`DDR_AXI.inst.IF);
77+
`TH.`SYS_CLK.inst.IF,
78+
`TH.`DMA_CLK.inst.IF,
79+
`TH.`DDR_CLK.inst.IF,
80+
`TH.`SYS_RST.inst.IF);
81+
82+
mng = new("", `TH.`MNG_AXI.inst.IF);
83+
ddr = new("", `TH.`DDR_AXI.inst.IF);
84+
85+
`LINK(mng, base_env, mng)
86+
`LINK(ddr, base_env, ddr)
7887

7988
dma_flock_env = new("DMA Flock Environment",
8089
`TH.`SRC_AXIS.inst.IF,
@@ -94,10 +103,10 @@ program test_program;
94103

95104
dma_flock_env.run();
96105

97-
m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA);
106+
m_dmac_api = new("TX_DMA_BA", base_env.mng.master_sequencer, `TX_DMA_BA);
98107
m_dmac_api.probe();
99108

100-
s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA);
109+
s_dmac_api = new("RX_DMA_BA", base_env.mng.master_sequencer, `RX_DMA_BA);
101110
s_dmac_api.probe();
102111

103112
sanity_test;
@@ -249,16 +258,16 @@ program test_program;
249258
bit [63:0] mtestWData; // Write Data
250259
bit [31:0] rdData;
251260

252-
base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
261+
base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
253262

254263
mtestWData = 0;
255264
repeat (10) begin
256-
base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
257-
base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
265+
base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
266+
base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
258267
mtestWData += 4;
259268
end
260269

261-
base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
270+
base_env.mng.master_sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
262271

263272
endtask
264273

‎testbenches/ip/dma_flock/tests/test_program_frame_delay.sv‎

Lines changed: 22 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
import logger_pkg::*;
3939
import environment_pkg::*;
4040
import test_harness_env_pkg::*;
41+
import adi_axi_agent_pkg::*;
4142
import adi_regmap_pkg::*;
4243
import adi_regmap_dmac_pkg::*;
4344
import dmac_api_pkg::*;
@@ -54,7 +55,11 @@ import `PKGIFY(test_harness, dst_axis_vip)::*;
5455
program test_program_frame_delay;
5556

5657
// declare the class instances
57-
test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env;
58+
test_harness_env base_env;
59+
60+
adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng;
61+
adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr;
62+
5863
dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env;
5964

6065
// Register accessors
@@ -72,12 +77,16 @@ program test_program_frame_delay;
7277

7378
//creating environment
7479
base_env = new("Base Environment",
75-
`TH.`SYS_CLK.inst.IF,
76-
`TH.`DMA_CLK.inst.IF,
77-
`TH.`DDR_CLK.inst.IF,
78-
`TH.`SYS_RST.inst.IF,
79-
`TH.`MNG_AXI.inst.IF,
80-
`TH.`DDR_AXI.inst.IF);
80+
`TH.`SYS_CLK.inst.IF,
81+
`TH.`DMA_CLK.inst.IF,
82+
`TH.`DDR_CLK.inst.IF,
83+
`TH.`SYS_RST.inst.IF);
84+
85+
mng = new("", `TH.`MNG_AXI.inst.IF);
86+
ddr = new("", `TH.`DDR_AXI.inst.IF);
87+
88+
`LINK(mng, base_env, mng)
89+
`LINK(ddr, base_env, ddr)
8190

8291
dma_flock_env = new("DMA Flock Environment",
8392
`TH.`SRC_AXIS.inst.IF,
@@ -99,10 +108,10 @@ program test_program_frame_delay;
99108

100109
dma_flock_env.run();
101110

102-
m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA);
111+
m_dmac_api = new("TX_DMA_BA", base_env.mng.master_sequencer, `TX_DMA_BA);
103112
m_dmac_api.probe();
104113

105-
s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA);
114+
s_dmac_api = new("RX_DMA_BA", base_env.mng.master_sequencer, `RX_DMA_BA);
106115
s_dmac_api.probe();
107116

108117

@@ -303,16 +312,16 @@ program test_program_frame_delay;
303312
bit [63:0] mtestWData; // Write Data
304313
bit [31:0] rdData;
305314

306-
base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
315+
base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
307316

308317
mtestWData = 0;
309318
repeat (10) begin
310-
base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
311-
base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
319+
base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
320+
base_env.mng.master_sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData);
312321
mtestWData += 4;
313322
end
314323

315-
base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
324+
base_env.mng.master_sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43);
316325

317326
endtask
318327

‎testbenches/ip/dma_loopback/tests/test_program.sv‎

Lines changed: 17 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
`include "axi_definitions.svh"
3838

3939
import test_harness_env_pkg::*;
40+
import adi_axi_agent_pkg::*;
4041
import logger_pkg::*;
4142
import adi_regmap_pkg::*;
4243
import adi_regmap_dmac_pkg::*;
@@ -49,7 +50,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*;
4950

5051
program test_program;
5152

52-
test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env;
53+
test_harness_env base_env;
54+
55+
adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng;
56+
adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr;
5357

5458
// Register accessors
5559
dmac_api m_dmac_api;
@@ -59,23 +63,27 @@ program test_program;
5963

6064
//creating environment
6165
base_env = new("Base Environment",
62-
`TH.`SYS_CLK.inst.IF,
63-
`TH.`DMA_CLK.inst.IF,
64-
`TH.`DDR_CLK.inst.IF,
65-
`TH.`SYS_RST.inst.IF,
66-
`TH.`MNG_AXI.inst.IF,
67-
`TH.`DDR_AXI.inst.IF);
66+
`TH.`SYS_CLK.inst.IF,
67+
`TH.`DMA_CLK.inst.IF,
68+
`TH.`DDR_CLK.inst.IF,
69+
`TH.`SYS_RST.inst.IF);
70+
71+
mng = new("", `TH.`MNG_AXI.inst.IF);
72+
ddr = new("", `TH.`DDR_AXI.inst.IF);
73+
74+
`LINK(mng, base_env, mng)
75+
`LINK(ddr, base_env, ddr)
6876

6977
setLoggerVerbosity(ADI_VERBOSITY_NONE);
7078

7179
base_env.start();
7280
start_clocks();
7381
base_env.sys_reset();
7482

75-
m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA);
83+
m_dmac_api = new("TX_DMA", base_env.mng.master_sequencer, `TX_DMA_BA);
7684
m_dmac_api.probe();
7785

78-
s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA);
86+
s_dmac_api = new("RX_DMA", base_env.mng.master_sequencer, `RX_DMA_BA);
7987
s_dmac_api.probe();
8088

8189
// -------------------------------------------------------

‎testbenches/ip/dma_sg/tests/test_program_1d.sv‎

Lines changed: 27 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737

3838
import logger_pkg::*;
3939
import test_harness_env_pkg::*;
40+
import adi_axi_agent_pkg::*;
4041
import adi_regmap_pkg::*;
4142
import adi_regmap_dmac_pkg::*;
4243
import dmac_api_pkg::*;
@@ -48,7 +49,10 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*;
4849

4950
program test_program_1d;
5051

51-
test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env;
52+
test_harness_env base_env;
53+
54+
adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng;
55+
adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr;
5256

5357
// Register accessors
5458
dmac_api m_dmac_api;
@@ -58,23 +62,27 @@ program test_program_1d;
5862

5963
// Creating environment
6064
base_env = new("Base Environment",
61-
`TH.`SYS_CLK.inst.IF,
62-
`TH.`DMA_CLK.inst.IF,
63-
`TH.`DDR_CLK.inst.IF,
64-
`TH.`SYS_RST.inst.IF,
65-
`TH.`MNG_AXI.inst.IF,
66-
`TH.`DDR_AXI.inst.IF);
65+
`TH.`SYS_CLK.inst.IF,
66+
`TH.`DMA_CLK.inst.IF,
67+
`TH.`DDR_CLK.inst.IF,
68+
`TH.`SYS_RST.inst.IF);
69+
70+
mng = new("", `TH.`MNG_AXI.inst.IF);
71+
ddr = new("", `TH.`DDR_AXI.inst.IF);
72+
73+
`LINK(mng, base_env, mng)
74+
`LINK(ddr, base_env, ddr)
6775

6876
setLoggerVerbosity(ADI_VERBOSITY_NONE);
6977

7078
base_env.start();
7179
`TH.`DEVICE_CLK.inst.IF.start_clock();
7280
base_env.sys_reset();
7381

74-
m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA);
82+
m_dmac_api = new("TX_DMA", base_env.mng.master_sequencer, `TX_DMA_BA);
7583
m_dmac_api.probe();
7684

77-
s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA);
85+
s_dmac_api = new("RX_DMA", base_env.mng.master_sequencer, `RX_DMA_BA);
7886
s_dmac_api.probe();
7987

8088
#1us;
@@ -187,25 +195,25 @@ program test_program_1d;
187195
dma_segment m_seg, s_seg;
188196
int m_tid, s_tid;
189197

190-
base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address
191-
base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC
198+
base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address
199+
base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC
192200
`SET_DMAC_CONTROL_HWDESC(1) |
193201
`SET_DMAC_CONTROL_ENABLE(1));
194-
base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags
202+
base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags
195203

196-
base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address
197-
base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC
204+
base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address
205+
base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC
198206
`SET_DMAC_CONTROL_HWDESC(1) |
199207
`SET_DMAC_CONTROL_ENABLE(1));
200-
base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags
208+
base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags
201209

202-
base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT),
210+
base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT),
203211
`SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1));
204-
base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT),
212+
base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT),
205213
`SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1));
206214

207-
base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address
208-
base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT),
215+
base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address
216+
base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT),
209217
`SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1));
210218

211219
m_dmac_api.transfer_id_get(m_tid);

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