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IstvanZsSzekelyIstvanZsSzekely
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SPI VIP update
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
1 parent 8ee0dee commit a5337ee

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17 files changed

+1612
-1532
lines changed

17 files changed

+1612
-1532
lines changed

‎library/includes/Makeinclude_spi_engine.mk‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@ include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
77

88
# All test-bench dependencies except test programs
99
SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/spi_vip/adi_spi_vip_pkg.sv
10-
SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/spi_vip/s_spi_sequencer.sv
1110
SV_DEPS += $(TB_LIBRARY_PATH)/drivers/spi_engine/spi_engine_instr_pkg.sv
1211
SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_spi_engine_pkg.sv
1312

‎library/includes/sp_include_spi_engine.tcl‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,6 @@ source $ad_tb_dir/library/includes/sp_include_regmap.tcl
3838
# Add test files to the project
3939
adi_sim_project_files [list \
4040
"$ad_tb_dir/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv" \
41-
"$ad_tb_dir/library/vip/adi/spi_vip/s_spi_sequencer.sv" \
4241
"$ad_tb_dir/library/drivers/spi_engine/spi_engine_instr_pkg.sv" \
4342
"$ad_tb_dir/library/regmaps/adi_regmap_spi_engine_pkg.sv" \
4443
]

‎library/vip/adi/io_vip/io_vip_ip.tcl‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,16 +15,21 @@ adi_ip_files io_vip [list \
1515
adi_ip_properties_lite io_vip
1616
adi_ip_sim_ttcl io_vip "io_vip_pkg.ttcl"
1717

18+
set cc [ipx::current_core]
19+
20+
set_property company_url {Unavailable} $cc
21+
22+
set_property display_name "ADI IO VIP" $cc
23+
set_property description "ADI IO Verification IP" $cc
24+
1825
# Remove all inferred interfaces
19-
ipx::remove_all_bus_interface [ipx::current_core]
26+
ipx::remove_all_bus_interface $cc
2027

2128
## Interface definitions
2229

2330
adi_set_ports_dependency "in" \
2431
"(spirit:decode(id('MODELPARAM_VALUE.MODE')) = 0)"
2532

26-
set cc [ipx::current_core]
27-
2833
## MODE
2934
set_property -dict [list \
3035
"value_validation_type" "pairs" \
@@ -35,11 +40,10 @@ set_property -dict [list \
3540
## Customize IP Layout
3641
## Remove the automatically generated GUI page
3742
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
38-
ipx::save_core [ipx::current_core]
39-
43+
ipx::save_core $cc
4044

4145
## Create general configuration page
42-
ipgui::add_page -name {IO VIP} -component [ipx::current_core] -display_name {IO VIP}
46+
ipgui::add_page -name {IO VIP} -component $cc -display_name {IO VIP}
4347
set page0 [ipgui::get_pagespec -name "IO VIP" -component $cc]
4448

4549
set general_group [ipgui::add_group -name "General Configuration" -component $cc \

‎library/vip/adi/spi_vip/Makefile‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,11 @@ include ../../../../scripts/make_tb_path.mk
99

1010
LIBRARY_NAME := adi_spi_vip
1111

12-
GENERIC_DEPS += $(TB_LIBRARY_PATH)/utilities/utils.svh
1312
GENERIC_DEPS += adi_spi_vip_pkg.sv
1413
GENERIC_DEPS += spi_vip_if.sv
1514
GENERIC_DEPS += adi_spi_vip.sv
1615

1716
XILINX_DEPS += adi_spi_vip_ip.tcl
18-
XILINX_DEPS += adi_spi_vip_pkg.ttcl
1917

2018
#TODO: INTEL_DEPS += adi_spi_vip_hw.tcl
2119

‎library/vip/adi/spi_vip/adi_spi_vip.sv‎

Lines changed: 18 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -33,8 +33,6 @@
3333
// ***************************************************************************
3434
// ***************************************************************************
3535

36-
`include "utils.svh"
37-
3836
module adi_spi_vip #(
3937
parameter MODE = 0, // SLAVE=0
4038
parameter CPOL = 0,
@@ -49,11 +47,11 @@ module adi_spi_vip #(
4947
parameter DEFAULT_MISO_DATA = 'hCAFE
5048
) (
5149
input logic s_spi_sclk,
52-
input wire s_spi_mosi,
50+
input logic s_spi_mosi,
5351
output wire s_spi_miso,
5452
input logic s_spi_cs,
5553
output logic m_spi_sclk,
56-
output wire m_spi_mosi,
54+
output logic m_spi_mosi,
5755
input wire m_spi_miso,
5856
output logic m_spi_cs
5957
);
@@ -76,41 +74,33 @@ module adi_spi_vip #(
7674
.DEFAULT_MISO_DATA (DEFAULT_MISO_DATA)
7775
) IF ();
7876

79-
initial begin : ASSERT_PARAMETERS
80-
assert (MODE == MODE_SLAVE)
81-
else begin
82-
$error("Unsupported mode %s. Valid values are 0=SLAVE, 1=MASTER, 2=MONITOR. Only 0(SLAVE) is currently supported.", MODE);
83-
end
84-
end : ASSERT_PARAMETERS
77+
if (MODE != MODE_SLAVE) begin
78+
$error("Unsupported mode %s. Valid values are 0=SLAVE, 1=MASTER, 2=MONITOR. Only 0(SLAVE) is currently supported.", MODE);
79+
end
8580

8681
generate
82+
83+
assign s_spi_miso = IF.s_miso;
84+
assign IF.s_mosi = s_spi_mosi;
85+
assign IF.s_cs = s_spi_cs;
86+
assign IF.s_sclk = s_spi_sclk;
87+
88+
assign IF.m_miso = m_spi_miso;
89+
assign m_spi_mosi = IF.m_mosi;
90+
assign m_spi_sclk = IF.m_sclk;
91+
assign m_spi_cs = IF.m_cs;
92+
8793
if (MODE == MODE_SLAVE) begin
88-
assign s_spi_miso = IF.miso;
89-
assign IF.mosi = s_spi_mosi;
90-
assign IF.sclk = s_spi_sclk;
91-
assign IF.cs = s_spi_cs;
9294
initial begin
9395
IF.set_slave_mode();
9496
end
9597
end else if (MODE == MODE_MASTER) begin
96-
assign IF.miso = m_spi_miso;
97-
assign m_spi_mosi = IF.mosi;
98-
assign m_spi_sclk = IF.sclk;
99-
assign m_spi_cs = IF.cs;
10098
initial begin
10199
IF.set_master_mode();
102100
end
103101
end else if (MODE == MODE_MONITOR) begin
104-
assign IF.miso = m_spi_miso;
105-
assign IF.mosi = s_spi_mosi;
106-
assign IF.miso = s_spi_miso;
107-
assign IF.cs = s_spi_cs;
108-
assign s_spi_miso = m_spi_miso;
109-
assign m_spi_mosi = s_spi_mosi;
110-
assign m_spi_sclk = s_spi_sclk;
111-
assign m_spi_cs = s_spi_cs;
112102
initial begin
113-
IF.intf_monitor_mode();
103+
IF.set_monitor_mode();
114104
end
115105
end
116106
endgenerate

library/vip/adi/spi_vip/s_spi_sequencer.sv renamed to library/vip/adi/spi_vip/adi_spi_vip_if_base_pkg.sv

Lines changed: 42 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
// ***************************************************************************
2-
// ***************************************************************************
3-
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
2+
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
43
//
54
// In this HDL repository, there are many different and unique modules, consisting
65
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -33,52 +32,59 @@
3332
// ***************************************************************************
3433
// ***************************************************************************
3534

36-
`include "utils.svh"
35+
package adi_spi_vip_if_base_pkg;
36+
37+
typedef enum {SPI_MODE_SLAVE, SPI_MODE_MASTER, SPI_MODE_MONITOR} spi_mode_t;
38+
39+
virtual class adi_spi_vip_if_base;
40+
41+
function new();
42+
endfunction
43+
44+
pure virtual function int get_param_MODE();
45+
46+
pure virtual function int get_param_CPOL();
47+
48+
pure virtual function int get_param_CPHA();
3749

38-
package s_spi_sequencer_pkg;
50+
pure virtual function int get_param_INV_CS();
3951

40-
import logger_pkg::*;
41-
import adi_common_pkg::*;
42-
import adi_spi_vip_pkg::*;
52+
pure virtual function int get_param_DATA_DLENGTH();
4353

44-
class s_spi_sequencer #(`SPI_VIP_PARAM_ORDER) extends adi_component;
54+
pure virtual function int get_param_SLAVE_TIN();
4555

46-
protected adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent;
56+
pure virtual function int get_param_SLAVE_TOUT();
4757

48-
function new(
49-
input string name,
50-
input adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent,
51-
input adi_component parent = null);
58+
pure virtual function int get_param_MASTER_TIN();
5259

53-
super.new(name, parent);
60+
pure virtual function int get_param_MASTER_TOUT();
5461

55-
this.agent = agent;
56-
endfunction: new
62+
pure virtual function int get_param_CS_TO_MISO();
5763

58-
virtual task automatic send_data(input int unsigned data);
59-
this.agent.send_data(data);
60-
endtask : send_data
64+
pure virtual function int get_param_DEFAULT_MISO_DATA();
6165

62-
virtual task automatic receive_data(output int unsigned data);
63-
this.agent.receive_data(data);
64-
endtask : receive_data
66+
pure virtual function spi_mode_t get_mode();
6567

66-
virtual task automatic receive_data_verify(input int unsigned expected);
67-
int unsigned received;
68-
this.agent.receive_data(received);
69-
if (received !== expected) begin
70-
this.error($sformatf("Data mismatch. Received : %h; expected %h", received, expected));
71-
end
72-
endtask : receive_data_verify
68+
pure virtual function logic get_cs_active();
7369

74-
virtual task flush_send();
75-
this.agent.flush_send();
76-
endtask : flush_send
70+
pure virtual task wait_cs_active();
7771

78-
virtual function void set_default_miso_data(input int unsigned data);
79-
this.agent.set_default_miso_data(data);
80-
endfunction : set_default_miso_data
72+
pure virtual task wait_cs_inactive();
8173

74+
pure virtual task wait_for_sample_edge();
75+
76+
pure virtual function logic get_mosi_delayed();
77+
78+
pure virtual task set_miso_drive(bit val);
79+
80+
pure virtual task set_miso_drive_instantaneous(bit val);
81+
82+
pure virtual task wait_for_drive_edge();
83+
84+
pure virtual task wait_cs();
85+
86+
pure virtual task set_miso_oen(bit val);
8287

8388
endclass
84-
endpackage
89+
90+
endpackage

‎library/vip/adi/spi_vip/adi_spi_vip_ip.tcl‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,21 +8,22 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
88

99
adi_ip_create adi_spi_vip
1010
adi_ip_files adi_spi_vip [list \
11-
"adi_spi_vip_pkg.sv" \
1211
"adi_spi_vip.sv" \
1312
"spi_vip_if.sv" \
14-
"adi_spi_vip_pkg.ttcl" \
15-
"$ad_tb_dir/library/utilities/utils.svh" \
16-
"$ad_tb_dir/library/utilities/logger_pkg.sv" \
13+
"adi_spi_vip_if_base_pkg.sv" \
1714
]
1815

1916
adi_ip_properties_lite adi_spi_vip
20-
adi_ip_sim_ttcl adi_spi_vip "adi_spi_vip_pkg.ttcl"
2117

22-
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine} [ipx::current_core]
18+
set cc [ipx::current_core]
19+
20+
set_property company_url {Unavailable} $cc
21+
22+
set_property display_name "ADI SPI VIP" $cc
23+
set_property description "ADI SPI Verification IP" $cc
2324

2425
# Remove all inferred interfaces
25-
ipx::remove_all_bus_interface [ipx::current_core]
26+
ipx::remove_all_bus_interface $cc
2627

2728
## Interface definitions
2829

@@ -52,8 +53,6 @@ adi_add_bus "m_spi" "master" \
5253

5354
## Parameter validations
5455

55-
set cc [ipx::current_core]
56-
5756
## MODE
5857
set_property -dict [list \
5958
"value_validation_type" "pairs" \
@@ -157,7 +156,7 @@ set_property -dict [list \
157156
## DEFAULT_MISO_DATA
158157
set_property -dict [list \
159158
"value_bit_string_length" "32" \
160-
"value_format" "bit_string" \
159+
"value_format" "bitString" \
161160
"enablement_tcl_expr" "\$MODE==0" \
162161
] \
163162
[ipx::get_user_parameters DEFAULT_MISO_DATA -of_objects $cc]

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