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ad57xx: add testbench (#122)
add a test for the ad57xx project, and also updates the spi engine tests to include sdo streaming for dac-type scenarios. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
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‎ad57xx/Makefile‎

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####################################################################################
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####################################################################################
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## Copyright 2024(c) Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# All test-bench dependencies except test programs
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SV_DEPS += ../common/sv/utils.svh
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SV_DEPS += ../common/sv/logger_pkg.sv
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SV_DEPS += ../common/sv/reg_accessor.sv
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SV_DEPS += ../common/sv/m_axis_sequencer.sv
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SV_DEPS += ../common/sv/s_axis_sequencer.sv
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SV_DEPS += ../common/sv/m_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_axi_sequencer.sv
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SV_DEPS += ../common/sv/s_spi_sequencer.sv
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SV_DEPS += ../common/sv/spi_vip/adi_spi_vip_pkg.sv
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SV_DEPS += ../common/sv/dmac_api.sv
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SV_DEPS += ../common/sv/adi_regmap_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_clkgen_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_spi_engine_pkg.sv
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SV_DEPS += ../common/sv/adi_regmap_pwm_gen_pkg.sv
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SV_DEPS += ../common/sv/dma_trans.sv
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SV_DEPS += ad57xx_environment.sv
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SV_DEPS += system_tb.sv
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ENV_DEPS += system_project.tcl
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ENV_DEPS += system_bd.tcl
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ENV_DEPS += ../scripts/adi_sim.tcl
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ENV_DEPS += ../scripts/run_sim.tcl
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += util_axis_fifo
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LIB_DEPS += spi_engine/axi_spi_engine
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LIB_DEPS += spi_engine/spi_engine_execution
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LIB_DEPS += spi_engine/spi_engine_interconnect
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LIB_DEPS += spi_engine/spi_engine_offload
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LIB_DEPS += sysid_rom
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SIM_LIB_DEPS += spi_vip
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# default test programs
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# Format is: <test name>
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TP := $(notdir $(basename $(wildcard tests/*.sv)))
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP)))
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include ../scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=cfg1 TST=test_program MODE=gui
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#
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# run all test from a configuration
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# make cfg1
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####################################################################################
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####################################################################################

‎ad57xx/README.md‎

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎ad57xx/ad57xx_environment.sv‎

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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`include "utils.svh"
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package ad57xx_environment_pkg;
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import axi_vip_pkg::*;
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import axi4stream_vip_pkg::*;
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import m_axi_sequencer_pkg::*;
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import s_axi_sequencer_pkg::*;
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import s_spi_sequencer_pkg::*;
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import adi_spi_vip_pkg::*;
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import test_harness_env_pkg::*;
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import `PKGIFY(test_harness, mng_axi_vip)::*;
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import `PKGIFY(test_harness, ddr_axi_vip)::*;
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import `PKGIFY(test_harness, spi_s_vip)::*;
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class ad57xx_environment extends test_harness_env;
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// Agents
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adi_spi_agent #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_agent;
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// Sequencers
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s_spi_sequencer #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_seq;
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//============================================================================
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// Constructor
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//============================================================================
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function new(
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if,
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if,
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if,
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virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if,
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virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if,
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virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if,
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virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if
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);
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super.new(sys_clk_vip_if,
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dma_clk_vip_if,
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ddr_clk_vip_if,
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sys_rst_vip_if,
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mng_vip_if,
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ddr_vip_if);
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// Creating the agents
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spi_agent = new(spi_s_vip_if);
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// Creating the sequencers
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spi_seq = new(spi_agent);
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endfunction
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//============================================================================
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// Start environment
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// - Connect all the agents to the scoreboard
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// - Start the agents
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//============================================================================
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task start();
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super.start();
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spi_agent.start();
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endtask
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//============================================================================
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// Start the test
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// - start the scoreboard
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// - start the sequencers
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//============================================================================
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task test();
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super.test();
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fork
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join_none
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endtask
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//============================================================================
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// Post test subroutine
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//============================================================================
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task post_test();
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super.post_test();
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endtask
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//============================================================================
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// Run subroutine
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//============================================================================
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task run;
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test();
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post_test();
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endtask
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//============================================================================
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// Stop subroutine
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//============================================================================
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task stop;
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spi_agent.stop();
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super.stop();
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endtask
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endclass
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endpackage

‎ad57xx/cfgs/cfg1.tcl‎

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global ad_project_params
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# SPI Engine DUT parameters
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set ad_project_params(DATA_WIDTH) 32
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set ad_project_params(ASYNC_SPI_CLK) 1
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set ad_project_params(NUM_OF_CS) 1
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set ad_project_params(NUM_OF_SDI) 1
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set ad_project_params(NUM_OF_SDO) 1
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set ad_project_params(SDI_DELAY) 1
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set ad_project_params(ECHO_SCLK) 0
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set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
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set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
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set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
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set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
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set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
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set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
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# Test parameters
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set ad_project_params(DATA_DLENGTH) 24
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set ad_project_params(THREE_WIRE) 0
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set ad_project_params(CPOL) 0
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set ad_project_params(CPHA) 1
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set ad_project_params(SDO_IDLE_STATE) 0
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set ad_project_params(SLAVE_TIN) 0
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set ad_project_params(SLAVE_TOUT) 0
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set ad_project_params(MASTER_TIN) 0
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set ad_project_params(MASTER_TOUT) 0
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set ad_project_params(CS_TO_MISO) 0
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set ad_project_params(CLOCK_DIVIDER) 1
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set ad_project_params(NUM_OF_WORDS) 1
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set ad_project_params(NUM_OF_TRANSFERS) 3
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set ad_project_params(CS_ACTIVE_HIGH) 0
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set ad_project_params(ECHO_SCLK_DELAY) 0.1
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set ad_project_params(PWM_PERIOD) 98
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set ad_project_params(TEST_DATA_MODE) DATA_MODE_PATTERN;
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set spi_s_vip_cfg [ list \
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MODE 0 \
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CPOL $ad_project_params(CPOL) \
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CPHA $ad_project_params(CPHA) \
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INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
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SLAVE_TIN $ad_project_params(SLAVE_TIN) \
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SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
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MASTER_TIN $ad_project_params(MASTER_TIN) \
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MASTER_TOUT $ad_project_params(MASTER_TOUT) \
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CS_TO_MISO $ad_project_params(CS_TO_MISO) \
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DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
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]
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set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg

‎ad57xx/system_bd.tcl‎

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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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global ad_project_params
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adi_project_files [list \
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"../../library/common/ad_edge_detect.v" \
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"../../library/util_cdc/sync_bits.v" \
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"../../library/common/ad_iobuf.v" \
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]
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#
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# Block design under test
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#
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source ../../projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl
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# Add test-specific VIPs
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ad_ip_instance adi_spi_vip spi_s_vip $ad_project_params(spi_s_vip_cfg)
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adi_sim_add_define "SPI_S=spi_s_vip"
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ad_disconnect ad57xx_spi spi_ad57xx/m_spi
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ad_connect spi_s_vip/s_spi spi_ad57xx/m_spi
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# Last tasks
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create_bd_port -dir O ad57xx_spi_clk
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create_bd_port -dir O ad57xx_spi_irq
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create_bd_port -dir O ad57xx_spi_sclk
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ad_connect ad57xx_spi_clk axi_ad57xx_clkgen/clk_0
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ad_connect ad57xx_spi_irq spi_ad57xx/irq
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set BA_SPI_REGMAP 0x44A00000
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set_property offset $BA_SPI_REGMAP [get_bd_addr_segs {mng_axi_vip/Master_AXI/spi_ad57xx_axi_regmap}]
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adi_sim_add_define "SPI_ENGINE_SPI_REGMAP_BA=[format "%d" ${BA_SPI_REGMAP}]"
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set BA_TX_DMA 0x44A40000
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set_property offset $BA_TX_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_ad57xx_dma}]
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adi_sim_add_define "SPI_ENGINE_TX_DMA_BA=[format "%d" ${BA_TX_DMA}]"
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set BA_CLKGEN 0x44A70000
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set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad57xx_clkgen}]
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adi_sim_add_define "SPI_ENGINE_AXI_CLKGEN_BA=[format "%d" ${BA_CLKGEN}]"
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set BA_PWM 0x44B00000
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set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_trig_gen}]
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adi_sim_add_define "SPI_ENGINE_PWM_GEN_BA=[format "%d" ${BA_PWM}]"

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