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LBFFilhoLBFFilho
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SPI Engine: improve test_sleep_delay (#110)
Check for sleep delay being affected by SPI word size (should not be affected) Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
1 parent e78ce4a commit 72e4ca8

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7 files changed

+65
-37
lines changed

7 files changed

+65
-37
lines changed

‎ad463x/tests/test_program.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ import test_harness_env_pkg::*;
5050
//---------------------------------------------------------------------------
5151
// SPI Engine configuration parameters
5252
//---------------------------------------------------------------------------
53-
localparam PCORE_VERSION = 32'h0001_0200;
53+
localparam PCORE_VERSION = 32'h0001_0201;
5454
localparam SAMPLE_PERIOD = 500;
5555
localparam ASYNC_SPI_CLK = 1;
5656
localparam DATA_WIDTH = 32;

‎ad7616/tests/test_program_si.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ import test_harness_env_pkg::*;
5050
//---------------------------------------------------------------------------
5151
// SPI Engine configuration parameters
5252
//---------------------------------------------------------------------------
53-
localparam PCORE_VERSION = 32'h0001_0200;
53+
localparam PCORE_VERSION = 32'h0001_0201;
5454
localparam SAMPLE_PERIOD = 500;
5555
localparam ASYNC_SPI_CLK = 1;
5656
localparam DATA_WIDTH = 16;

‎common/sv/adi_regmap_spi_engine_pkg.sv‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
// ***************************************************************************
3434
// ***************************************************************************
3535
/* Auto generated Register Map */
36-
/* Thu Mar 28 13:22:23 2024 */
36+
/* Tue Jun 25 17:14:36 2024 */
3737

3838
package adi_regmap_spi_engine_pkg;
3939
import adi_regmap_pkg::*;
@@ -42,9 +42,9 @@ package adi_regmap_spi_engine_pkg;
4242
/* SPI Engine (axi_spi_engine) */
4343

4444
const reg_t AXI_SPI_ENGINE_VERSION = '{ 'h0000, "VERSION" , '{
45-
"VERSION_MAJOR": '{ 31, 16, RO, 'h01 },
46-
"VERSION_MINOR": '{ 15, 8, RO, 'h02 },
47-
"VERSION_PATCH": '{ 7, 0, RO, 'h0 }}};
45+
"VERSION_MAJOR": '{ 31, 16, RO, 'h00000001 },
46+
"VERSION_MINOR": '{ 15, 8, RO, 'h00000002 },
47+
"VERSION_PATCH": '{ 7, 0, RO, 'h00000001 }}};
4848
`define SET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) SetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
4949
`define GET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) GetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
5050
`define DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR GetResetValue(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR")
@@ -66,7 +66,7 @@ package adi_regmap_spi_engine_pkg;
6666
`define UPDATE_AXI_SPI_ENGINE_PERIPHERAL_ID_PERIPHERAL_ID(x,y) UpdateField(AXI_SPI_ENGINE_PERIPHERAL_ID,"PERIPHERAL_ID",x,y)
6767

6868
const reg_t AXI_SPI_ENGINE_SCRATCH = '{ 'h0008, "SCRATCH" , '{
69-
"SCRATCH": '{ 31, 0, RW, 'h0 }}};
69+
"SCRATCH": '{ 31, 0, RW, 'h00000000 }}};
7070
`define SET_AXI_SPI_ENGINE_SCRATCH_SCRATCH(x) SetField(AXI_SPI_ENGINE_SCRATCH,"SCRATCH",x)
7171
`define GET_AXI_SPI_ENGINE_SCRATCH_SCRATCH(x) GetField(AXI_SPI_ENGINE_SCRATCH,"SCRATCH",x)
7272
`define DEFAULT_AXI_SPI_ENGINE_SCRATCH_SCRATCH GetResetValue(AXI_SPI_ENGINE_SCRATCH,"SCRATCH")
@@ -85,8 +85,8 @@ package adi_regmap_spi_engine_pkg;
8585
`define UPDATE_AXI_SPI_ENGINE_DATA_WIDTH_DATA_WIDTH(x,y) UpdateField(AXI_SPI_ENGINE_DATA_WIDTH,"DATA_WIDTH",x,y)
8686

8787
const reg_t AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH = '{ 'h0010, "OFFLOAD_MEM_ADDR_WIDTH" , '{
88-
"SDO_MEM_ADDRESS_WIDTH": '{ 15, 8, RO, 'h04 },
89-
"CMD_MEM_ADDRESS_WIDTH": '{ 7, 0, RO, 'h04 }}};
88+
"SDO_MEM_ADDRESS_WIDTH": '{ 15, 8, RO, 'h00000004 },
89+
"CMD_MEM_ADDRESS_WIDTH": '{ 7, 0, RO, 'h00000004 }}};
9090
`define SET_AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH_SDO_MEM_ADDRESS_WIDTH(x) SetField(AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH,"SDO_MEM_ADDRESS_WIDTH",x)
9191
`define GET_AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH_SDO_MEM_ADDRESS_WIDTH(x) GetField(AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH,"SDO_MEM_ADDRESS_WIDTH",x)
9292
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH_SDO_MEM_ADDRESS_WIDTH GetResetValue(AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH,"SDO_MEM_ADDRESS_WIDTH")
@@ -97,10 +97,10 @@ package adi_regmap_spi_engine_pkg;
9797
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH_CMD_MEM_ADDRESS_WIDTH(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD_MEM_ADDR_WIDTH,"CMD_MEM_ADDRESS_WIDTH",x,y)
9898

9999
const reg_t AXI_SPI_ENGINE_FIFO_ADDR_WIDTH = '{ 'h0014, "FIFO_ADDR_WIDTH" , '{
100-
"SDI_FIFO_ADDRESS_WIDTH": '{ 31, 24, RO, 'h05 },
101-
"SDO_FIFO_ADDRESS_WIDTH": '{ 23, 16, RO, 'h05 },
102-
"SYNC_FIFO_ADDRESS_WIDTH": '{ 15, 8, RO, 'h04 },
103-
"CMD_FIFO_ADDRESS_WIDTH": '{ 7, 0, RO, 'h04 }}};
100+
"SDI_FIFO_ADDRESS_WIDTH": '{ 31, 24, RO, 'h00000005 },
101+
"SDO_FIFO_ADDRESS_WIDTH": '{ 23, 16, RO, 'h00000005 },
102+
"SYNC_FIFO_ADDRESS_WIDTH": '{ 15, 8, RO, 'h00000004 },
103+
"CMD_FIFO_ADDRESS_WIDTH": '{ 7, 0, RO, 'h00000004 }}};
104104
`define SET_AXI_SPI_ENGINE_FIFO_ADDR_WIDTH_SDI_FIFO_ADDRESS_WIDTH(x) SetField(AXI_SPI_ENGINE_FIFO_ADDR_WIDTH,"SDI_FIFO_ADDRESS_WIDTH",x)
105105
`define GET_AXI_SPI_ENGINE_FIFO_ADDR_WIDTH_SDI_FIFO_ADDRESS_WIDTH(x) GetField(AXI_SPI_ENGINE_FIFO_ADDR_WIDTH,"SDI_FIFO_ADDRESS_WIDTH",x)
106106
`define DEFAULT_AXI_SPI_ENGINE_FIFO_ADDR_WIDTH_SDI_FIFO_ADDRESS_WIDTH GetResetValue(AXI_SPI_ENGINE_FIFO_ADDR_WIDTH,"SDI_FIFO_ADDRESS_WIDTH")
@@ -119,18 +119,18 @@ package adi_regmap_spi_engine_pkg;
119119
`define UPDATE_AXI_SPI_ENGINE_FIFO_ADDR_WIDTH_CMD_FIFO_ADDRESS_WIDTH(x,y) UpdateField(AXI_SPI_ENGINE_FIFO_ADDR_WIDTH,"CMD_FIFO_ADDRESS_WIDTH",x,y)
120120

121121
const reg_t AXI_SPI_ENGINE_ENABLE = '{ 'h0040, "ENABLE" , '{
122-
"ENABLE": '{ 31, 0, RW, 'h1 }}};
122+
"ENABLE": '{ 31, 0, RW, 'h00000001 }}};
123123
`define SET_AXI_SPI_ENGINE_ENABLE_ENABLE(x) SetField(AXI_SPI_ENGINE_ENABLE,"ENABLE",x)
124124
`define GET_AXI_SPI_ENGINE_ENABLE_ENABLE(x) GetField(AXI_SPI_ENGINE_ENABLE,"ENABLE",x)
125125
`define DEFAULT_AXI_SPI_ENGINE_ENABLE_ENABLE GetResetValue(AXI_SPI_ENGINE_ENABLE,"ENABLE")
126126
`define UPDATE_AXI_SPI_ENGINE_ENABLE_ENABLE(x,y) UpdateField(AXI_SPI_ENGINE_ENABLE,"ENABLE",x,y)
127127

128128
const reg_t AXI_SPI_ENGINE_IRQ_MASK = '{ 'h0080, "IRQ_MASK" , '{
129-
"CMD_ALMOST_EMPTY": '{ 0, 0, RW, 'h0 },
130-
"SDO_ALMOST_EMPTY": '{ 1, 1, RW, 'h0 },
131-
"SDI_ALMOST_FULL": '{ 2, 2, RW, 'h0 },
132-
"SYNC_EVENT": '{ 3, 3, RW, 'h0 },
133-
"OFFLOAD_SYNC_ID_PENDING": '{ 4, 4, RW, 'h0 }}};
129+
"CMD_ALMOST_EMPTY": '{ 0, 0, RW, 'h00000000 },
130+
"SDO_ALMOST_EMPTY": '{ 1, 1, RW, 'h00000000 },
131+
"SDI_ALMOST_FULL": '{ 2, 2, RW, 'h00000000 },
132+
"SYNC_EVENT": '{ 3, 3, RW, 'h00000000 },
133+
"OFFLOAD_SYNC_ID_PENDING": '{ 4, 4, RW, 'h00000000 }}};
134134
`define SET_AXI_SPI_ENGINE_IRQ_MASK_CMD_ALMOST_EMPTY(x) SetField(AXI_SPI_ENGINE_IRQ_MASK,"CMD_ALMOST_EMPTY",x)
135135
`define GET_AXI_SPI_ENGINE_IRQ_MASK_CMD_ALMOST_EMPTY(x) GetField(AXI_SPI_ENGINE_IRQ_MASK,"CMD_ALMOST_EMPTY",x)
136136
`define DEFAULT_AXI_SPI_ENGINE_IRQ_MASK_CMD_ALMOST_EMPTY GetResetValue(AXI_SPI_ENGINE_IRQ_MASK,"CMD_ALMOST_EMPTY")
@@ -153,14 +153,14 @@ package adi_regmap_spi_engine_pkg;
153153
`define UPDATE_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(x,y) UpdateField(AXI_SPI_ENGINE_IRQ_MASK,"OFFLOAD_SYNC_ID_PENDING",x,y)
154154

155155
const reg_t AXI_SPI_ENGINE_IRQ_PENDING = '{ 'h0084, "IRQ_PENDING" , '{
156-
"IRQ_PENDING": '{ 31, 0, RW1C, 'h0 }}};
156+
"IRQ_PENDING": '{ 31, 0, RW1C, 'h00000000 }}};
157157
`define SET_AXI_SPI_ENGINE_IRQ_PENDING_IRQ_PENDING(x) SetField(AXI_SPI_ENGINE_IRQ_PENDING,"IRQ_PENDING",x)
158158
`define GET_AXI_SPI_ENGINE_IRQ_PENDING_IRQ_PENDING(x) GetField(AXI_SPI_ENGINE_IRQ_PENDING,"IRQ_PENDING",x)
159159
`define DEFAULT_AXI_SPI_ENGINE_IRQ_PENDING_IRQ_PENDING GetResetValue(AXI_SPI_ENGINE_IRQ_PENDING,"IRQ_PENDING")
160160
`define UPDATE_AXI_SPI_ENGINE_IRQ_PENDING_IRQ_PENDING(x,y) UpdateField(AXI_SPI_ENGINE_IRQ_PENDING,"IRQ_PENDING",x,y)
161161

162162
const reg_t AXI_SPI_ENGINE_IRQ_SOURCE = '{ 'h0088, "IRQ_SOURCE" , '{
163-
"IRQ_SOURCE": '{ 31, 0, RO, 'h0 }}};
163+
"IRQ_SOURCE": '{ 31, 0, RO, 'h00000000 }}};
164164
`define SET_AXI_SPI_ENGINE_IRQ_SOURCE_IRQ_SOURCE(x) SetField(AXI_SPI_ENGINE_IRQ_SOURCE,"IRQ_SOURCE",x)
165165
`define GET_AXI_SPI_ENGINE_IRQ_SOURCE_IRQ_SOURCE(x) GetField(AXI_SPI_ENGINE_IRQ_SOURCE,"IRQ_SOURCE",x)
166166
`define DEFAULT_AXI_SPI_ENGINE_IRQ_SOURCE_IRQ_SOURCE GetResetValue(AXI_SPI_ENGINE_IRQ_SOURCE,"IRQ_SOURCE")
@@ -174,7 +174,7 @@ package adi_regmap_spi_engine_pkg;
174174
`define UPDATE_AXI_SPI_ENGINE_SYNC_ID_SYNC_ID(x,y) UpdateField(AXI_SPI_ENGINE_SYNC_ID,"SYNC_ID",x,y)
175175

176176
const reg_t AXI_SPI_ENGINE_OFFLOAD_SYNC_ID = '{ 'h00c4, "OFFLOAD_SYNC_ID" , '{
177-
"OFFLOAD_SYNC_ID": '{ 31, 0, RO, 'h0 }}};
177+
"OFFLOAD_SYNC_ID": '{ 31, 0, RO, 'h00000000 }}};
178178
`define SET_AXI_SPI_ENGINE_OFFLOAD_SYNC_ID_OFFLOAD_SYNC_ID(x) SetField(AXI_SPI_ENGINE_OFFLOAD_SYNC_ID,"OFFLOAD_SYNC_ID",x)
179179
`define GET_AXI_SPI_ENGINE_OFFLOAD_SYNC_ID_OFFLOAD_SYNC_ID(x) GetField(AXI_SPI_ENGINE_OFFLOAD_SYNC_ID,"OFFLOAD_SYNC_ID",x)
180180
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD_SYNC_ID_OFFLOAD_SYNC_ID GetResetValue(AXI_SPI_ENGINE_OFFLOAD_SYNC_ID,"OFFLOAD_SYNC_ID")
@@ -195,7 +195,7 @@ package adi_regmap_spi_engine_pkg;
195195
`define UPDATE_AXI_SPI_ENGINE_SDO_FIFO_ROOM_SDO_FIFO_ROOM(x,y) UpdateField(AXI_SPI_ENGINE_SDO_FIFO_ROOM,"SDO_FIFO_ROOM",x,y)
196196

197197
const reg_t AXI_SPI_ENGINE_SDI_FIFO_LEVEL = '{ 'h00d8, "SDI_FIFO_LEVEL" , '{
198-
"SDI_FIFO_LEVEL": '{ 31, 0, RO, 'h0 }}};
198+
"SDI_FIFO_LEVEL": '{ 31, 0, RO, 'h00000000 }}};
199199
`define SET_AXI_SPI_ENGINE_SDI_FIFO_LEVEL_SDI_FIFO_LEVEL(x) SetField(AXI_SPI_ENGINE_SDI_FIFO_LEVEL,"SDI_FIFO_LEVEL",x)
200200
`define GET_AXI_SPI_ENGINE_SDI_FIFO_LEVEL_SDI_FIFO_LEVEL(x) GetField(AXI_SPI_ENGINE_SDI_FIFO_LEVEL,"SDI_FIFO_LEVEL",x)
201201
`define DEFAULT_AXI_SPI_ENGINE_SDI_FIFO_LEVEL_SDI_FIFO_LEVEL GetResetValue(AXI_SPI_ENGINE_SDI_FIFO_LEVEL,"SDI_FIFO_LEVEL")
@@ -237,21 +237,21 @@ package adi_regmap_spi_engine_pkg;
237237
`define UPDATE_AXI_SPI_ENGINE_SDI_FIFO_PEEK_SDI_FIFO_PEEK(x,y) UpdateField(AXI_SPI_ENGINE_SDI_FIFO_PEEK,"SDI_FIFO_PEEK",x,y)
238238

239239
const reg_t AXI_SPI_ENGINE_OFFLOAD0_EN = '{ 'h0100, "OFFLOAD0_EN" , '{
240-
"OFFLOAD0_EN": '{ 31, 0, RW, 'h0 }}};
240+
"OFFLOAD0_EN": '{ 31, 0, RW, 'h00000000 }}};
241241
`define SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_EN,"OFFLOAD0_EN",x)
242242
`define GET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_EN,"OFFLOAD0_EN",x)
243243
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_EN,"OFFLOAD0_EN")
244244
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_EN,"OFFLOAD0_EN",x,y)
245245

246246
const reg_t AXI_SPI_ENGINE_OFFLOAD0_STATUS = '{ 'h0104, "OFFLOAD0_STATUS" , '{
247-
"OFFLOAD0_STATUS": '{ 31, 0, RO, 'h0 }}};
247+
"OFFLOAD0_STATUS": '{ 31, 0, RO, 'h00000000 }}};
248248
`define SET_AXI_SPI_ENGINE_OFFLOAD0_STATUS_OFFLOAD0_STATUS(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_STATUS,"OFFLOAD0_STATUS",x)
249249
`define GET_AXI_SPI_ENGINE_OFFLOAD0_STATUS_OFFLOAD0_STATUS(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_STATUS,"OFFLOAD0_STATUS",x)
250250
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_STATUS_OFFLOAD0_STATUS GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_STATUS,"OFFLOAD0_STATUS")
251251
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_STATUS_OFFLOAD0_STATUS(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_STATUS,"OFFLOAD0_STATUS",x,y)
252252

253253
const reg_t AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET = '{ 'h0108, "OFFLOAD0_MEM_RESET" , '{
254-
"OFFLOAD0_MEM_RESET": '{ 31, 0, WO, 'h0 }}};
254+
"OFFLOAD0_MEM_RESET": '{ 31, 0, WO, 'h00000000 }}};
255255
`define SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET",x)
256256
`define GET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET",x)
257257
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET")

‎pulsar_adc_pmdz/tests/test_program.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ import test_harness_env_pkg::*;
5151
//---------------------------------------------------------------------------
5252
// SPI Engine configuration parameters
5353
//---------------------------------------------------------------------------
54-
localparam PCORE_VERSION = 32'h0001_0200;
54+
localparam PCORE_VERSION = 32'h0001_0201;
5555
localparam SAMPLE_PERIOD = 500;
5656
localparam ASYNC_SPI_CLK = 1;
5757
localparam DATA_WIDTH = 32;

‎pulsar_adc_pmdz/tests/test_sleep_delay.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ import test_harness_env_pkg::*;
4949
//---------------------------------------------------------------------------
5050
// SPI Engine configuration parameters
5151
//---------------------------------------------------------------------------
52-
localparam PCORE_VERSION = 32'h0001_0200;
52+
localparam PCORE_VERSION = 32'h0001_0201;
5353
localparam SAMPLE_PERIOD = 500;
5454
localparam ASYNC_SPI_CLK = 1;
5555
localparam DATA_WIDTH = 32;

‎spi_engine/tests/test_program.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ import adi_spi_vip_pkg::*;
5252
//---------------------------------------------------------------------------
5353
// SPI Engine configuration parameters
5454
//---------------------------------------------------------------------------
55-
localparam PCORE_VERSION = 32'h0001_0200;
55+
localparam PCORE_VERSION = 32'h0001_0201;
5656

5757
program test_program (
5858
inout spi_engine_irq,

‎spi_engine/tests/test_sleep_delay.sv‎

Lines changed: 36 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ import adi_spi_vip_pkg::*;
5050
//---------------------------------------------------------------------------
5151
// SPI Engine configuration parameters
5252
//---------------------------------------------------------------------------
53-
localparam PCORE_VERSION = 32'h0001_0200;
53+
localparam PCORE_VERSION = 32'h0001_0201;
5454

5555
program test_sleep_delay (
5656
inout spi_engine_irq,
@@ -212,9 +212,13 @@ end
212212
//---------------------------------------------------------------------------
213213

214214
int sleep_instr_time[$];
215+
int sleep_duration;
215216
int sleep_current_duration;
217+
bit sleeping;
216218
int cs_instr_time[$];
217219
int cs_current_duration;
220+
int cs_duration;
221+
bit cs_sleeping;
218222
wire [15:0] cmd, cmd_d1;
219223
wire cmd_valid, cmd_ready;
220224
wire idle;
@@ -227,23 +231,34 @@ assign idle = `TH.spi_engine.spi_engine_execution.inst.idle;
227231

228232
initial begin
229233
sleep_current_duration = 0;
234+
sleep_duration = 0;
235+
sleeping = 1'b0;
236+
cs_current_duration = 0;
237+
cs_duration = 0;
238+
cs_sleeping = 1'b0;
230239
forever begin
231240
@(posedge spi_engine_spi_clk);
232-
if (idle && (cmd_d1[15:8] == 8'h31)) begin
241+
if (idle && (cmd_d1[15:8] == 8'h31) && sleeping) begin
242+
sleeping <= 1'b0;
243+
sleep_duration = sleep_current_duration+1;
233244
sleep_instr_time.push_front(sleep_current_duration+1); // add one to account for this cycle
234245
end
235246
if (cmd_valid && cmd_ready && (cmd[15:8] == 8'h31)) begin
236-
sleep_current_duration = 0;
247+
sleep_current_duration <= 0;
248+
sleeping <= 1'b1;
237249
end else begin
238-
sleep_current_duration = sleep_current_duration+1;
250+
sleep_current_duration <= sleep_current_duration+1;
239251
end
240-
if (idle && (cmd_d1[15:10] == 6'h4)) begin
252+
if (idle && (cmd_d1[15:10] == 6'h4) && cs_sleeping) begin
253+
cs_sleeping = 1'b0;
254+
cs_duration = cs_current_duration+1;
241255
cs_instr_time.push_front(cs_current_duration+1); // add one to account for this cycle
242256
end
243257
if (cmd_valid && cmd_ready && (cmd[15:10] == 6'h4)) begin
244-
cs_current_duration = 0;
258+
cs_current_duration <= 0;
259+
cs_sleeping <= 1'b1;
245260
end else begin
246-
cs_current_duration = cs_current_duration+1;
261+
cs_current_duration <= cs_current_duration+1;
247262
end
248263
end
249264
end
@@ -281,7 +296,7 @@ task sleep_delay_test(
281296
// Write commands
282297
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG);
283298
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE);
284-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH);
299+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), ((`INST_DLENGTH) & 32'hFFFF_FF00) | 16);
285300
if (`CS_ACTIVE_HIGH) begin
286301
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `cs_inv_mask(8'hFF));
287302
end
@@ -297,6 +312,19 @@ task sleep_delay_test(
297312
end else begin
298313
`INFO(("Sleep Test PASSED"));
299314
end
315+
316+
// change the SPI word size (this should not affect sleep delay)
317+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH);
318+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`sleep(sleep_param)));
319+
#2000ns
320+
sleep_time = sleep_instr_time.pop_back();
321+
#100ns
322+
if ((sleep_time != expected_sleep_time)) begin
323+
`ERROR(("Sleep Test FAILED: unexpected sleep instruction duration. Expected=%d, Got=%d",expected_sleep_time,sleep_time));
324+
end else begin
325+
`INFO(("Sleep Test PASSED"));
326+
end
327+
300328
// Disable SPI Engine
301329
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), 1);
302330
endtask

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