Add device tree for ADAQ23875. Add one lane support for CN0577

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq23875.dts

@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices LTC2387-16/ADAQ23875
+ *
+ * hdl_project: <cn0577/zed with make parameter ADC_RES=16>
+ * for all config modes, please check the README of the HDL project
+ * board_revision: <A>
+ *
+ * Copyright (C) 2022 - 2025 Analog Devices Inc.
+ */
+/dts-v1/;
+
+#include "zynq-zed.dtsi"
+#include "zynq-zed-adv7511.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	vref: regulator-vref {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply";
+		regulator-min-microvolt = <4096000>;
+		regulator-max-microvolt = <4096000>;
+		regulator-always-on;
+	};
+
+	clocks {
+		ext_clk: clock@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <120000000>;
+		};
+	};
+	gpio-control@0 {
+		compatible = "adi,one-bit-adc-dac";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		out-gpios = <&gpio0 86 GPIO_ACTIVE_HIGH>,
+			    <&gpio0 87 GPIO_ACTIVE_HIGH>;
+		channel@0 {
+			reg = <0>;
+			label = "adaq23875_testpat";
+		};
+		channel@1 {
+			reg = <1>;
+			label = "adaq23875_pd";
+		};
+	};
+};
+
+&fpga_axi {
+	rx_dma: dma-controller@44a30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44a30000 0x1000>;
+		#dma-cells = <1>;
+		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <16>;
+				adi,source-bus-type = <2>;
+				adi,destination-bus-width = <64>;
+				adi,destination-bus-type = <0>;
+			};
+		};
+	};
+
+	axi_pwm_gen: pwm@44a60000 {
+		compatible = "adi,axi-pwmgen-2.00.a";
+		reg = <0x44a60000 0x1000>;
+		label = "adaq23875_if";
+		#pwm-cells = <2>;
+		clocks = <&clkc 15>, <&ext_clk>;
+		clock-names = "axi", "ext";
+	};
+
+	adaq23875@0{
+		compatible = "adaq23875";
+		clocks = <&ext_clk>;
+		dmas = <&rx_dma 0>;
+		dma-names = "rx";
+		pwms = <&axi_pwm_gen 0 0
+			&axi_pwm_gen 1 0>;
+		pwm-names = "cnv", "clk_en";
+		vref-supply = <&vref>;
+
+		// uncomment the below command to use in one lane mode
+		// adi,use-one-lane;
+	};
+};

arch/arm/boot/dts/xilinx/zynq-zed-adv7511-cn0577.dts

@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Analog Devices LTC2387
+ * Analog Devices LTC2387-18/ADAQ23878
  *
  * hdl_project: <cn0577/zed>
+ * for all config modes, please check the README of the HDL project
  * board_revision: <A>
  *
- * Copyright (C) 2022 Analog Devices Inc.
+ * Copyright (C) 2022 - 2025 Analog Devices Inc.
  */
 /dts-v1/;
 
@@ -54,6 +55,19 @@
 		#dma-cells = <1>;
 		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc 15>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <32>;
+				adi,source-bus-type = <2>;
+				adi,destination-bus-width = <64>;
+				adi,destination-bus-type = <0>;
+			};
+		};
 	};
 
 	axi_pwm_gen: pwm@44a60000 {
@@ -75,6 +89,7 @@
 		pwm-names = "cnv", "clk_en";
 		vref-supply = <&vref>;
 
-		adi,use-two-lanes;
+		// uncomment the below command to use in one lane mode
+		// adi,use-one-lane;
 	};
 };

drivers/iio/adc/ltc2387.c

@@ -222,10 +222,13 @@
 	struct ltc2387_dev *ltc = iio_priv(indio_dev);
 	struct device *dev = indio_dev->dev.parent;
 
-	if (device_property_present(dev, "adi,use-two-lanes"))
+	if (device_property_present(dev, "adi,use-one-lane")) {
+		ltc->lane_mode = ONE_LANE;
+		return ltc2387_set_sampling_freq(ltc, 7.5 * MHz);
+	} else {
 		ltc->lane_mode = TWO_LANES;
-
-	return ltc2387_set_sampling_freq(ltc, 15 * MHz);
+		return ltc2387_set_sampling_freq(ltc, 15 * MHz);
+	}
 }
 
 static int ltc2387_read_raw(struct iio_dev *indio_dev,
@@ -242,7 +245,7 @@
 		return IIO_VAL_INT;
 	case IIO_CHAN_INFO_SCALE:
 		temp = regulator_get_voltage(ltc->vref);
 		if (temp < 0)
 			return temp;
 
 		*val = (temp * 2) / 1000;