Skip to content

Conversation

@taimur-10xe
Copy link
Collaborator

readme update to point to FPGA binaries repo.

sohaibimran-10xe pushed a commit that referenced this pull request Aug 21, 2024
* RTL Modifications for AE and AWB

* Bug Fixing for 3A in RTL

* Pylint error fixing

* Moved AWB before WB module

* Bug Fixing for AWB-3A

* RTl Modifications in AE

* Made pixel limit calculated through approximations

* Restoration of YUV image from 422 and 444 formats

* Bug Fixing in restore YUV Function

* Bug Fixing for 3A

* Rolled Back YUV changes

* 3A BUG FIXING

* modified automation file according to new position
of AWB in isp_pipeline and generated test vector.

* Removed Linting Errors.

* modified automation file with no linting errors.

* Finalized Code for YUV Format Conversion

* Removed Linting Errors

* resolved linting errors and removed test_func file from
util.

* Removed AE Redundant Code

* Bug Fixing in AE

* Removed wbg_gen.py

---------

Co-authored-by: Maria_Nadeem-10x <maria.nadeem@10xengineers.ai>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants