Format all files, introduce small upgrades.

Author: lsteiner-tukl

.clang-format

@@ -0,0 +1,11 @@
+AccessModifierOffset: '-4'
+AllowShortFunctionsOnASingleLine: InlineOnly
+AllowShortIfStatementsOnASingleLine: Never
+BinPackArguments: 'false'
+BinPackParameters: 'false'
+BreakBeforeBraces: Allman
+BreakConstructorInitializers: AfterColon
+ColumnLimit: '100'
+IndentWidth: '4'
+PackConstructorInitializers: CurrentLine
+PointerAlignment: Left

.clang-tidy

@@ -0,0 +1,18 @@
+Checks: > 
+  clang-diagnostic-*,
+  clang-analyzer-*,
+  modernize-*,
+  bugprone-*,
+  concurrency-*,
+  cppcoreguidelines-*,
+  performance-*,
+  portability-*,
+  readability-*,
+  -modernize-use-trailing-return-type,
+  -readability-braces-around-statements,
+  -readability-identifier-length,
+  -readability-function-cognitive-complexity
+WarningsAsErrors: ''
+HeaderFilterRegex: ''
+AnalyzeTemporaryDtors: false
+FormatStyle: file

CMakePresets.json

@@ -69,7 +69,8 @@
                 "std"
             ],
             "cacheVariables": {
-                "CMAKE_BUILD_TYPE": "Debug"
+                "CMAKE_BUILD_TYPE": "Debug",
+                "CMAKE_CXX_FLAGS": "-Wall -Wextra -Wpedantic"
             }
         }
     ]

README.md

@@ -10,22 +10,29 @@ This is the public read-only mirror of an internal DRAMSys repository. Pull requ
 
 The user DOES NOT get ANY WARRANTIES when using this tool. This software is released under the BSD 3-Clause License. By using this software, the user implicitly agrees to the licensing terms.
 
-If you decide to use DRAMSys in your research please cite the papers [2] [3]. To cite the TLM methodology of DRAMSys use the paper [1].
+If you decide to use DRAMSys in your research please cite the paper [2] or [3]. To cite the TLM methodology of DRAMSys use the paper [1].
 
-## Key Features
+## Included Features
 
-- **Standalone** simulator with trace players and traffic generators, **gem5**-coupled simulator and **TLM-AT-compliant library**
-- Support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2**
-- Support for **DDR5**, **LPDDR5** and **HBM3** (please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) 
-- Automatic source code generation for new JEDEC standards [3] [9] from DRAMml DSL
+- **Standalone** simulator with trace players and traffic generators or **TLM-2.0-compliant library**
+- Coupling to **gem5** supported
+- Cycle-accurate **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2** modelling
+- Bit-granular address mapping with optional XOR connections [7]
 - Various scheduling policies
 - Open, closed and adaptive page policies [8]
-- All-bank, same-bank, per-bank and per-2-bank refresh
+- All-bank, same-bank, per-bank and per-2-bank refresh, postponed and pulled in refresh commands
+- Refresh management
 - Staggered power down [5]
-- Coupling to **DRAMPower** [4] and for power simulation
+- Coupling to **DRAMPower** [4] for power simulation
+
+## Additional Features
+
+- Cycle-accurate **DDR5**, **LPDDR5** and **HBM3** modelling
 - **Trace Analyzer** for visual and metric-based result analysis
+- **Free academic** or **commercial** licenses available (please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information)
 
 ## Video
+
 The linked video shows the background of DRAMSys and some examples of how simulations can be performed.
 
 [![DRAMSys Video](https://img.youtube.com/vi/xdfaGv7MPVo/0.jpg)](https://www.youtube.com/watch?v=xdfaGv7MPVo)
@@ -125,12 +132,12 @@ Christian Weis
 [1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration  
 M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
 
-[2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework  
-M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
-
-[3] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator  
+[2] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator  
 L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece.
 
+[3] DRAMSys4.0: An Open-Source Simulation Framework for In-Depth DRAM Analyses
+L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2022.
+
 [4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool  
 K. Chandrasekar, C. Weis, Y. Li, S. Goossens, M. Jung, O. Naji, B. Akesson, N. Wehn, K. Goossens. URL: http://www.drampower.info
 
@@ -140,8 +147,8 @@ M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. VLSI-SoC, October, 2014, Playa d
 [6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs  
 C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.
 
-[7] ConGen: An Application Specific DRAM Memory Controller Generator  
-M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
+[7] Efficient Generation of Application Specific Memory Controllers
+M. V. Natale, M. Jung, K. Kraft, F. Lauer, J. Feldmann, C. Sudarshan, C. Weis, S. O. Krumke, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2020), October, 2020, virtual conference.
 
 [8] Simulating DRAM controllers for future system architecture exploration  
 A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, A. N. Udipi. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014, Monterey, USA.

configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json

@@ -15,6 +15,7 @@
         "memoryType": "LPDDR4",
         "memtimingspec": {
             "CCD": 8,
+            "CCDMW": 32,
             "CKE": 4,
             "CMDCKE": 3,
             "DQS2DQ": 0,

configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json

@@ -15,6 +15,7 @@
         "memoryType": "LPDDR4",
         "memtimingspec": {
             "CCD": 8,
+            "CCDMW": 32,
             "CKE": 4,
             "CMDCKE": 3,
             "DQS2DQ": 0,

configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json

@@ -15,6 +15,7 @@
         "memoryType": "LPDDR4",
         "memtimingspec": {
             "CCD": 8,
+            "CCDMW": 32,
             "CKE": 6,
             "CMDCKE": 3,
             "DQS2DQ": 0,

configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json

@@ -15,6 +15,7 @@
         "memoryType": "LPDDR4",
         "memtimingspec": {
             "CCD": 8,
+            "CCDMW": 32,
             "CKE": 9,
             "CMDCKE": 3,
             "DQS2DQ": 0,

configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json

@@ -15,6 +15,7 @@
         "memoryType": "LPDDR4",
         "memtimingspec": {
             "CCD": 8,
+            "CCDMW": 32,
             "CKE": 10,
             "CMDCKE": 3,
             "DQS2DQ": 0,

configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json

@@ -15,6 +15,7 @@
         "memoryType": "LPDDR4",
         "memtimingspec": {
             "CCD": 8,
+            "CCDMW": 32,
             "CKE": 12,
             "CMDCKE": 3,
             "DQS2DQ": 0,