Formatting, SerDes interface.

Author: lsteiner-tukl

.gitattributes

@@ -1,4 +1,5 @@
 *.stl filter=lfs diff=lfs merge=lfs -text
+configs/traces/*.stl -filter=lfs -diff=lfs -merge=lfs -text
 *.data.gz filter=lfs diff=lfs merge=lfs -text
 *.inst.gz filter=lfs diff=lfs merge=lfs -text
 *.tdb filter=lfs diff=lfs merge=lfs -text

.gitignore

@@ -27,3 +27,4 @@ DRAMSys/docs/doxygen
 cmake-build*
 .idea
 .cache
+.env

CMakeLists.txt

@@ -28,7 +28,7 @@
 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: 
+# Authors:
 #    Thomas Psota
 #    Lukas Steiner
 
@@ -125,15 +125,19 @@ if(DRAMSYS_BUILD_TESTS)
 endif()
 
 ### SystemC ###
-list(APPEND CMAKE_PREFIX_PATH $ENV{SYSTEMC_HOME} /opt/systemc/)
+list(APPEND CMAKE_PREFIX_PATH $ENV{SYSTEMC_HOME})
 FetchContent_Declare(
     systemc
     GIT_REPOSITORY https://github.com/accellera-official/systemc.git
     GIT_TAG 2.3.4
     FIND_PACKAGE_ARGS NAMES SystemCLanguage)
 
 set(DISABLE_COPYRIGHT_MESSAGE True)
-FetchContent_MakeAvailable(systemc)
+
+# Allow populating of a user-set SystemC package
+if (NOT TARGET SystemC::systemc)
+    FetchContent_MakeAvailable(systemc)
+endif()
 
 ### DRAMPower ###
 if (DRAMSYS_WITH_DRAMPOWER)

README.md

@@ -1,4 +1,4 @@
-<img src="docs/images/dramsys_logo.png" width="350" style="float: left;" alt="DRAMSys Logo"/>  
+<img src="docs/images/dramsys_logo.png" width="350" style="float: left;" alt="DRAMSys Logo"/>
 
 **DRAMSys** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed by the [Microelectronic Systems Design Research Group](https://eit.rptu.de/en/fgs/ems/home/seite) at [RPTU Kaiserslautern-Landau](https://rptu.de/en/), by [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html) and by the [Computer Engineering Group](https://www.informatik.uni-wuerzburg.de/ce/) at [JMU Würzburg](https://www.uni-wuerzburg.de/en/home/).
 
@@ -39,19 +39,19 @@ The linked video shows the background of DRAMSys and some examples of how simula
 
 ## Trace Analyzer Consulting and Custom-Tailored Modifications
 
-To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer. 
+To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer.
 
 All requests, responses and DRAM commands can be recorded in an SQLite trace database during a simulation and visualized with the tool afterwards. An evaluation of the trace databases can be performed with the powerful Python interface of the Trace Analyzer. Different metrics are described as SQL statements and formulas in Python, which can be customized or extended without recompilation.
 
 The Trace Analyzer's main window is shown below.
 
 If you are interested in the Trace Analyzer, if you need support with the setup of DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
 
-![Trace Analyzer Main Window](docs/images/traceanalyzer.png) 
+![Trace Analyzer Main Window](docs/images/traceanalyzer.png)
 
 ## Basic Setup
 
-To use DRAMSys, first clone the repository. Make sure that Git LFS is installed on your machine.
+To use DRAMSys, first clone the repository.
 
 ### Dependencies
 
@@ -103,55 +103,67 @@ There are two ways to couple DRAMSys with **gem5**:
 - Use the official integration of DRAMSys in gem5. More information can be found in `ext/dramsys` of the gem5 repository.
 - (Deprecated) Compile gem5 as a shared library and link it with DRAMSys, which is only supported in older versions of DRAMSys (tag v4.0).
 
+## Development
+Some additional development sources required for tests may be obtained using Git LFS.
+Make sure to have Git LFS installed through your system's package manager and set up for your user:
+```bash
+git lfs install
+```
+
+To make the additional files available, run:
+```bash
+git lfs pull
+```
+
 ## Acknowledgements
 
-The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development. 
-
-Shama Bhosale  
-Derek Christ  
-Luiza Correa  
-Peter Ehses  
-Johannes Feldmann  
-Robert Gernhardt  
-Doris Gulai  
-Matthias Jung  
-Frederik Lauer  
-Ana Mativi  
-Felipe S. Prado  
-Iron Prando  
-Tran Anh Quoc  
-Janik Schlemminger  
-Lukas Steiner  
-Thanh C. Tran  
-Norbert Wehn  
-Christian Weis  
+The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development.
+
+Shama Bhosale
+Derek Christ
+Luiza Correa
+Peter Ehses
+Johannes Feldmann
+Robert Gernhardt
+Doris Gulai
+Matthias Jung
+Frederik Lauer
+Ana Mativi
+Felipe S. Prado
+Iron Prando
+Tran Anh Quoc
+Janik Schlemminger
+Lukas Steiner
+Thanh C. Tran
+Norbert Wehn
+Christian Weis
 Éder F. Zulian
 
 ## References
 
-[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration  
+[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
 M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
 
-[2] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator  
+[2] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
 L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece.
 
 [3] DRAMSys4.0: An Open-Source Simulation Framework for In-Depth DRAM Analyses
 L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2022.
 
-[4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool  
+[4] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
 K. Chandrasekar, C. Weis, Y. Li, S. Goossens, M. Jung, O. Naji, B. Akesson, N. Wehn, K. Goossens. URL: http://www.drampower.info
 
-[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs  
+[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
 M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini. VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
 
-[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs  
+[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
 C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.
 
 [7] Efficient Generation of Application Specific Memory Controllers
 M. V. Natale, M. Jung, K. Kraft, F. Lauer, J. Feldmann, C. Sudarshan, C. Weis, S. O. Krumke, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2020), October, 2020, virtual conference.
 
-[8] Simulating DRAM controllers for future system architecture exploration  
+[8] Simulating DRAM controllers for future system architecture exploration
 A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, A. N. Udipi. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014, Monterey, USA.
 
-[9] Fast Validation of DRAM Protocols with Timed Petri Nets  
+[9] Fast Validation of DRAM Protocols with Timed Petri Nets
 M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.

configs/simconfig/gem5_se.json

@@ -5,7 +5,7 @@
         "DatabaseRecording": true,
         "Debug": false,
         "EnableWindowing": true,
-        "PowerAnalysis": true,
+        "PowerAnalysis": false,
         "SimulationName": "gem5_se",
         "SimulationProgressBar": true,
         "StoreMode": "Store",

requirements.txt

@@ -0,0 +1,4 @@
+matplotlib
+numpy
+pyvcd
+tqdm

src/libdramsys/DRAMSys/common/Deserialize.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2023, RPTU Kaiserslautern-Landau
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author:
+ *    Derek Christ
+ */
+
+#ifndef DEDESERIALIZE_H
+#define DEDESERIALIZE_H
+
+#include <istream>
+
+namespace DRAMSys
+{
+class Deserialize
+{
+protected:
+    Deserialize() = default;
+    Deserialize(const Deserialize&) = default;
+    Deserialize(Deserialize&&) = default;
+    Deserialize& operator=(const Deserialize&) = default;
+    Deserialize& operator=(Deserialize&&) = default;
+
+public:
+    virtual ~Deserialize() = default;
+
+    virtual void deserialize(std::istream& stream) = 0;
+};
+
+} // namespace DRAMSys
+
+#endif

src/libdramsys/DRAMSys/common/Serialize.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2023, RPTU Kaiserslautern-Landau
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author:
+ *    Derek Christ
+ */
+
+#ifndef SERIALIZE_H
+#define SERIALIZE_H
+
+#include <ostream>
+
+namespace DRAMSys
+{
+class Serialize
+{
+protected:
+    Serialize() = default;
+    Serialize(const Serialize&) = default;
+    Serialize(Serialize&&) = default;
+    Serialize& operator=(const Serialize&) = default;
+    Serialize& operator=(Serialize&&) = default;
+
+public:
+    virtual ~Serialize() = default;
+
+    virtual void serialize(std::ostream& stream) const = 0;
+};
+
+} // namespace DRAMSys
+
+#endif

src/libdramsys/DRAMSys/controller/Controller.cpp

@@ -273,6 +273,16 @@ Controller::Controller(const sc_module_name& name,
         SC_REPORT_FATAL("Controller", "Selected refresh mode not supported!");
 }
 
+bool Controller::idle() const
+{
+    return totalNumberOfPayloads == 0;
+}
+
+void Controller::registerIdleCallback(std::function<void()> idleCallback)
+{
+    this->idleCallback = std::move(idleCallback);
+}
+
 void Controller::controllerMethod()
 {
     if (isFullCycle(sc_time_stamp(), memSpec.tCK))
@@ -575,6 +585,11 @@ void Controller::manageResponses()
             if (totalNumberOfPayloads == 0)
             {
                 idleTimeCollector.start();
+
+                if (idleCallback)
+                {
+                    idleCallback();
+                }
             }
         }
         else

src/libdramsys/DRAMSys/controller/Controller.h

@@ -48,6 +48,7 @@
 #include <stack>
 #include <systemc>
 #include <tlm>
+#include <utility>
 #include <vector>
 
 namespace DRAMSys
@@ -61,6 +62,9 @@ class Controller : public ControllerIF
                const AddressDecoder& addressDecoder);
     SC_HAS_PROCESS(Controller);
 
+    [[nodiscard]] bool idle() const override;
+    void registerIdleCallback(std::function<void()> idleCallback);
+
 protected:
     tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
                                        tlm::tlm_phase& phase,
@@ -88,6 +92,7 @@ class Controller : public ControllerIF
 
 private:
     unsigned totalNumberOfPayloads = 0;
+    std::function<void()> idleCallback;
     ControllerVector<Rank, unsigned> ranksNumberOfPayloads;
     ReadyCommands readyCommands;