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lines changed Original file line number Diff line number Diff line change 99)
1010
1111const (
12- cpuFreq = 125 * MHz
12+ cpuFreq = 200 * MHz
1313 _NUMBANK0_GPIOS = 30
1414 _NUMBANK0_IRQS = 4
1515 _NUMIRQ = 32
@@ -208,3 +208,16 @@ func (clks *clocksType) initTicks() {} // No ticks on RP2040
208208func (wd * watchdogImpl ) startTick (cycles uint32 ) {
209209 rp .WATCHDOG .TICK .Set (cycles | rp .WATCHDOG_TICK_ENABLE )
210210}
211+
212+ func adjustCoreVoltage () bool {
213+ if cpuFreq <= 133 * MHz {
214+ return false
215+ }
216+ // The rp2040 is certified to run at 200MHz with the
217+ // core voltage set to 1150mV.
218+ const targetVoltage = 1150
219+ // 0b0101 maps to 800mV and each step is 50mV.
220+ const vreg = 0b0101 + (targetVoltage - 800 )/ 50
221+ rp .VREG_AND_CHIP_RESET .SetVREG_VSEL (vreg )
222+ return true
223+ }
Original file line number Diff line number Diff line change @@ -222,3 +222,7 @@ func EnterBootloader() {
222222func (wd * watchdogImpl ) startTick (cycles uint32 ) {
223223 rp .TICKS .WATCHDOG_CTRL .SetBits (1 )
224224}
225+
226+ func adjustCoreVoltage () bool {
227+ return false
228+ }
Original file line number Diff line number Diff line change @@ -42,6 +42,10 @@ type clock struct {
4242 cix clockIndex
4343}
4444
45+ // The delay in seconds for core voltage adjustments to
46+ // settle. Taken from the Pico SDK.
47+ const _VREG_VOLTAGE_AUTO_ADJUST_DELAY = 1 / 1e3
48+
4549// clock returns the clock identified by cix.
4650func (clks * clocksType ) clock (cix clockIndex ) clock {
4751 return clock {
@@ -188,6 +192,14 @@ func (clks *clocksType) init() {
188192 xoscFreq ,
189193 xoscFreq )
190194
195+ if adjustCoreVoltage () {
196+ // Wait for the voltage to settle.
197+ const cycles = _VREG_VOLTAGE_AUTO_ADJUST_DELAY * xoscFreq * MHz
198+ for i := 0 ; i < cycles ; i ++ {
199+ arm .Asm ("nop" )
200+ }
201+ }
202+
191203 // clkSys = pllSys (125MHz) / 1 = 125MHz
192204 csys := clks .clock (clkSys )
193205 csys .configure (rp .CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX ,
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