1+ // Copyright [2021] <tiansongyu>
2+
13#include " Mapper_001.h"
24
35Mapper_001::Mapper_001 (uint8_t prgBanks, uint8_t chrBanks)
@@ -99,24 +101,24 @@ bool Mapper_001::cpuMapWrite(uint16_t addr, uint32_t &mapped_addr,
99101 // Sets the switchable PRG ROM bank to the value of A.;
100102 // ;
101103 // A MMC1_SR MMC1_PB
102- // setPRGBank:;
104+ // setPRGBank:;
103105 // 000edcba 10000 Start with an empty shift register(SR).The 1 is used
104- // sta $E000;
106+ // sta $E000;
105107 // 000edcba->a1000 to detect when the SR has become full.lsr a;
106108 // > 0000edcb a1000
107- // sta $E000;
109+ // sta $E000;
108110 // 0000edcb->ba100
109- // lsr a;
111+ // lsr a;
110112 // > 00000edc ba100
111- // sta $E000;
113+ // sta $E000;
112114 // 00000edc->cba10
113- // lsr a;
115+ // lsr a;
114116 // > 000000ed cba10
115- // sta $E000;
117+ // sta $E000;
116118 // 000000ed->dcba1 Once a 1 is shifted into the last position, the SR is
117- // full.lsr a; > 0000000e dcba1 sta $E000; 0000000e dcba1->edcba A write
118- // with the SR full copies D0 and the SR to a bank register; 10000($E000 -
119- // $FFFF means PRG bank number) and then clears the SR.rts
119+ // full.lsr a; > 0000000e dcba1 sta $E000; 0000000e dcba1->edcba
120+ // A write with the SR full copies D0 and the SR to a bank register;
121+ // 10000($E000 - $FFFF means PRG bank number) and then clears the SR.rts
120122
121123 nLoadRegister >>= 1 ;
122124 nLoadRegister |= (data & 0x01 ) << 4 ;
@@ -126,9 +128,8 @@ bool Mapper_001::cpuMapWrite(uint16_t addr, uint32_t &mapped_addr,
126128 // Get Mapper Target Register, by examining
127129 // bits 13 & 14 of the address
128130 uint8_t nTargetRegister = (addr >> 13 ) & 0x03 ;
129-
130- if (nTargetRegister == 0 ) // 0x8000 - 0x9FFF
131- {
131+ // 0x8000 - 0x9FFF
132+ if (nTargetRegister == 0 ) {
132133 // Set Control Register
133134 nControlRegister = nLoadRegister & 0x1F ;
134135
@@ -146,8 +147,7 @@ bool Mapper_001::cpuMapWrite(uint16_t addr, uint32_t &mapped_addr,
146147 mirrormode = HORIZONTAL;
147148 break ;
148149 }
149- } else if (nTargetRegister == 1 ) // 0xA000 - 0xBFFF
150- {
150+ } else if (nTargetRegister == 1 ) { // 0xA000 - 0xBFFF
151151 // Set CHR Bank Lo
152152 if (nControlRegister & 0b10000 ) {
153153 // 4K CHR Bank at PPU 0x0000
@@ -156,15 +156,13 @@ bool Mapper_001::cpuMapWrite(uint16_t addr, uint32_t &mapped_addr,
156156 // 8K CHR Bank at PPU 0x0000
157157 nCHRBankSelect8 = nLoadRegister & 0x1E ;
158158 }
159- } else if (nTargetRegister == 2 ) // 0xC000 - 0xDFFF
160- {
159+ } else if (nTargetRegister == 2 ) { // 0xC000 - 0xDFFF
161160 // Set CHR Bank Hi
162161 if (nControlRegister & 0b10000 ) {
163162 // 4K CHR Bank at PPU 0x1000
164163 nCHRBankSelect4Hi = nLoadRegister & 0x1F ;
165164 }
166- } else if (nTargetRegister == 3 ) // 0xE000 - 0xFFFF
167- {
165+ } else if (nTargetRegister == 3 ) { // 0xE000 - 0xFFFF
168166 // Configure PRG Banks
169167 uint8_t nPRGMode = (nControlRegister >> 2 ) & 0x03 ;
170168
@@ -250,4 +248,4 @@ void Mapper_001::reset() {
250248 nPRGBankSelect16Hi = nPRGBanks - 1 ;
251249}
252250
253- MIRROR Mapper_001::mirror () { return mirrormode; }
251+ MIRROR Mapper_001::mirror () { return mirrormode; }
0 commit comments