From 0225e12586c4df7a193cf7cd815625d957972654 Mon Sep 17 00:00:00 2001 From: Peter Enderborg Date: Mon, 24 Nov 2025 13:01:48 +0100 Subject: [PATCH] LINK_TYPE_DSA_GSW1XX: add EDSA protocol for GSW1xx family. For use of MaxLinear GSW1xx DSA driver in Linux. --- htmlsrc/linktypes.html | 11 ++ .../linktypes/LINKTYPE_DSA_TAG_GSW1XX.html | 30 ++++ htmlsrc/linktypes/gsw1xx-switch-tag.html | 91 +++++++++++ linktypes.html | 11 ++ linktypes/LINKTYPE_DSA_TAG_GSW1XX.html | 90 +++++++++++ linktypes/gsw1xx-switch-tag.html | 151 ++++++++++++++++++ regen_html_pages.sh | 3 + 7 files changed, 387 insertions(+) create mode 100644 htmlsrc/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html create mode 100644 htmlsrc/linktypes/gsw1xx-switch-tag.html create mode 100644 linktypes/LINKTYPE_DSA_TAG_GSW1XX.html create mode 100644 linktypes/gsw1xx-switch-tag.html diff --git a/htmlsrc/linktypes.html b/htmlsrc/linktypes.html index 0a24a261..607d3528 100644 --- a/htmlsrc/linktypes.html +++ b/htmlsrc/linktypes.html @@ -1937,6 +1937,17 @@

+ +LINKTYPE_DSA_TAG_GSW1XX +302 +DLT_DSA_TAG_GSW1XX + +Ethernet +frames, with a MaxLinear/Intel/Infinion switch tag inserted. + + + + LINKTYPE_IEEE802_15_4_TAP 283 diff --git a/htmlsrc/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html b/htmlsrc/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html new file mode 100644 index 00000000..6872977b --- /dev/null +++ b/htmlsrc/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html @@ -0,0 +1,30 @@ + +
+

+ LINKTYPE_DSA_TAG_GSW1XX +

+
+

Packet structure

+ 
++--------------------------------+
+| Destination Address (6 octets) |
++--------------------------------+
+|    Source Address (6 octets)   |
++--------------------------------+
+|   GSW1XX switch tag (8 octets) |
++--------------------------------+
+|   EtherType/Length (2 octets)  |
++--------------------------------+
+|            Payload             |
+.                                .
+.                                .
+.                                .
+
+

Description

+

+ A GSW1XX switch tag + is inserted in the Ethernet header before the EtherType/Length field. +

+
+
+ diff --git a/htmlsrc/linktypes/gsw1xx-switch-tag.html b/htmlsrc/linktypes/gsw1xx-switch-tag.html new file mode 100644 index 00000000..dcca94f1 --- /dev/null +++ b/htmlsrc/linktypes/gsw1xx-switch-tag.html @@ -0,0 +1,91 @@ + +
+

gsw1xx

+
+ The protocol + is used by GSW120, GSW140, GSW141, GSW145 chips and has a history with products from Infineon, Intel and MaxLinear. + The protocol information is based on the MaxLinear Data Sheet Revision 1.4. +

Switch tag structure

+
    + The gsw1xx EDSA tagged frames contain a proprietary tag inserted between the source address field and the + EtherType/length field in the Ethernet header. + The EDSA tag is 8 octets. It contains a programmable EtherType value + and a standard DSA tag. + Ingress and Egress have different formats. If byte 6&7 is not + zero it is a egress packet. +
+ Format of (Ethertyped) Ingress tagged frames: + 
+ +0 +----+----+----+----+----+----+----+----+  +-
+    |    Prog. DSA Ether Type [15:8]        |  | (8-byte) EDSA Tag
+ +1 +----+----+----+----+----+----+----+----+  | Contains a programmable Ether type.
+    |    Prog. DSA Ether Type [7:0]         |  |  +
+ +1 +----+----+----+----+----+----+----+----+  |  | (6-byte) Special Tag Content
+    |PME[7] TCE[6] TSE[5] FNL[4]   TTC[3:0] |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |         TEPML [7:0]                   |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |         TEPMH [7:0]                   |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |   Res[7:5]  IE[4]  SP[3:0]            |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |          Res [7:0] all zero           |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |          Res [7:0] all zero           |  |  |
+ +1 +----+----+----+----+----+----+----+----+  +- +-
+
+ Format of (Ethertyped) Egress tagged frames: + 
+
+ +0 +----+----+----+----+----+----+----+----+  +-
+    |    Prog. DSA Ether Type [15:8]        |  | (8-byte) EDSA Tag
+ +1 +----+----+----+----+----+----+----+----+  | Contains a programmable Ether type.
+    |    Prog. DSA Ether Type [7:0]         |  |  +
+ +1 +----+----+----+----+----+----+----+----+  |  | (6-byte) Special Tag Content
+    |        TC[7:4]    IPN [3:0]           |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    | PPPOE[7] IPV[6]   IPO[5:0]            |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |             DLPML [7:0]               |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |             DLPMR [7:0]               |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |  MI[7]  KL2UM[6] PLHB[5:0]            |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |             PLLB [7:0]                |  |  |
+ +1 +----+----+----+----+----+----+----+----+  +- +-
+
+
+
+

Bit field abbreviations

+
    +
  • PME: Port map enable
    • +
  • IPN: Ingress port number
    • +
  • TCE: Traffic class enable
    • +
  • TSE: Time stamp enable
    • +
  • FNL: Force no learning
    • +
  • TC: Traffic class
    • +
  • IPV: IPv4 packet
    • +
  • IPO: IP offset
    • +
  • SP: Source port
    • +
  • IE: Interrupt enable
    • +
  • PPPOE: ppp-over-ethernet
    • +
  • DLPML: Destination logical port map low bits.
    • +
  • DLPMR: Destination logical port map high (reserved)
    • +
  • MI: Mirror indication
    • +
  • KL2UM Known l2 unicast/multicast mac.
    • +
  • PLHB: Packet Length High Bits
    • +
  • PLLB: Packet Length Low Bits
    • +
  • TEPML: Target egress port maps low bits
    • +
  • TEPMH: Target egress port maps high bits (reserved)
    • +
  • Res: Reserved
    • +
+
+
Notes
+ Port mapping is a switch internal function for multi-cast and vlan + routing and need custom firmware rules to be active. +

+ Precise Time Stamping indication according to IEEE 1588v2. +
+
+ diff --git a/linktypes.html b/linktypes.html index b874678a..948f518c 100644 --- a/linktypes.html +++ b/linktypes.html @@ -1981,6 +1981,17 @@

+ +LINKTYPE_DSA_TAG_GSW1XX +302 +DLT_DSA_TAG_GSW1XX + +Ethernet +frames, with a MaxLinear/Intel/Infinion switch tag inserted. + + + + LINKTYPE_IEEE802_15_4_TAP 283 diff --git a/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html b/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html new file mode 100644 index 00000000..39f36ffc --- /dev/null +++ b/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html @@ -0,0 +1,90 @@ + + + + + + + LINKTYPE_DSA_TAG_GSW1XX | TCPDUMP & LIBPCAP + + + + + + + + + + + + + + +
+
+
+ + + + +
+ + +
+

+ LINKTYPE_DSA_TAG_GSW1XX +

+
+

Packet structure

+ 
++--------------------------------+
+| Destination Address (6 octets) |
++--------------------------------+
+|    Source Address (6 octets)   |
++--------------------------------+
+|   GSW1XX switch tag (8 octets) |
++--------------------------------+
+|   EtherType/Length (2 octets)  |
++--------------------------------+
+|            Payload             |
+.                                .
+.                                .
+.                                .
+
+

Description

+

+ A GSW1XX switch tag + is inserted in the Ethernet header before the EtherType/Length field. +

+
+
+ +
+ + + + + + + + + diff --git a/linktypes/gsw1xx-switch-tag.html b/linktypes/gsw1xx-switch-tag.html new file mode 100644 index 00000000..ce164da8 --- /dev/null +++ b/linktypes/gsw1xx-switch-tag.html @@ -0,0 +1,151 @@ + + + + + + + GSW1XX switch tag | TCPDUMP & LIBPCAP + + + + + + + + + + + + + + +
+
+
+ + + + +
+ + +
+

gsw1xx

+
+ The protocol + is used by GSW120, GSW140, GSW141, GSW145 chips and has a history with products from Infineon, Intel and MaxLinear. + The protocol information is based on the MaxLinear Data Sheet Revision 1.4. +

Switch tag structure

+
    + The gsw1xx EDSA tagged frames contain a proprietary tag inserted between the source address field and the + EtherType/length field in the Ethernet header. + The EDSA tag is 8 octets. It contains a programmable EtherType value + and a standard DSA tag. + Ingress and Egress have different formats. If byte 6&7 is not + zero it is a egress packet. +
+ Format of (Ethertyped) Ingress tagged frames: + 
+ +0 +----+----+----+----+----+----+----+----+  +-
+    |    Prog. DSA Ether Type [15:8]        |  | (8-byte) EDSA Tag
+ +1 +----+----+----+----+----+----+----+----+  | Contains a programmable Ether type.
+    |    Prog. DSA Ether Type [7:0]         |  |  +
+ +1 +----+----+----+----+----+----+----+----+  |  | (6-byte) Special Tag Content
+    |PME[7] TCE[6] TSE[5] FNL[4]   TTC[3:0] |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |         TEPML [7:0]                   |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |         TEPMH [7:0]                   |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |   Res[7:5]  IE[4]  SP[3:0]            |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |          Res [7:0] all zero           |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |          Res [7:0] all zero           |  |  |
+ +1 +----+----+----+----+----+----+----+----+  +- +-
+
+ Format of (Ethertyped) Egress tagged frames: + 
+
+ +0 +----+----+----+----+----+----+----+----+  +-
+    |    Prog. DSA Ether Type [15:8]        |  | (8-byte) EDSA Tag
+ +1 +----+----+----+----+----+----+----+----+  | Contains a programmable Ether type.
+    |    Prog. DSA Ether Type [7:0]         |  |  +
+ +1 +----+----+----+----+----+----+----+----+  |  | (6-byte) Special Tag Content
+    |        TC[7:4]    IPN [3:0]           |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    | PPPOE[7] IPV[6]   IPO[5:0]            |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |             DLPML [7:0]               |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |             DLPMR [7:0]               |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |  MI[7]  KL2UM[6] PLHB[5:0]            |  |  |
+ +1 +----+----+----+----+----+----+----+----+  |  |
+    |             PLLB [7:0]                |  |  |
+ +1 +----+----+----+----+----+----+----+----+  +- +-
+
+
+
+

Bit field abbreviations

+
    +
  • PME: Port map enable
    • +
  • IPN: Ingress port number
    • +
  • TCE: Traffic class enable
    • +
  • TSE: Time stamp enable
    • +
  • FNL: Force no learning
    • +
  • TC: Traffic class
    • +
  • IPV: IPv4 packet
    • +
  • IPO: IP offset
    • +
  • SP: Source port
    • +
  • IE: Interrupt enable
    • +
  • PPPOE: ppp-over-ethernet
    • +
  • DLPML: Destination logical port map low bits.
    • +
  • DLPMR: Destination logical port map high (reserved)
    • +
  • MI: Mirror indication
    • +
  • KL2UM Known l2 unicast/multicast mac.
    • +
  • PLHB: Packet Length High Bits
    • +
  • PLLB: Packet Length Low Bits
    • +
  • TEPML: Target egress port maps low bits
    • +
  • TEPMH: Target egress port maps high bits (reserved)
    • +
  • Res: Reserved
    • +
+
+
Notes
+ Port mapping is a switch internal function for multi-cast and vlan + routing and need custom firmware rules to be active. +

+ Precise Time Stamping indication according to IEEE 1588v2. +
+
+ +
+ + + + + + + + + diff --git a/regen_html_pages.sh b/regen_html_pages.sh index 95424f2a..0b1e2e30 100755 --- a/regen_html_pages.sh +++ b/regen_html_pages.sh @@ -89,6 +89,9 @@ substitute_page_title() marvell-switch-tag) title='Marvell switch tag | ' ;; + gsw1xx-switch-tag) + title='GSW1XX switch tag | ' + ;; netanalyzer-header) title='netANALYZER header | ' ;;