Ccdr does not need to consume PowerConfiguration

Author: usbalbin

examples/blinky.rs

@@ -22,7 +22,7 @@ fn main() -> ! {
 
     // Constrain and Freeze clock
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(250.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(250.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
     let mut led = gpioa.pa5.into_push_pull_output();

examples/dma.rs

@@ -24,7 +24,7 @@ fn main() -> ! {
 
     // Constrain and Freeze clock
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(250.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(250.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     let channels = dp.GPDMA1.channels(ccdr.peripheral.GPDMA1);
 

examples/dwt-blinky.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     // Constrain and Freeze clock
     info!("Setup RCC...                  ");
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(250.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(250.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
     let mut led = gpioa.pa5.into_push_pull_output();

examples/fractional-pll.rs

@@ -31,7 +31,7 @@ fn main() -> ! {
         .pll2_r_ck(3_024_000.Hz())
         // pll2_p / 2 --> mco2
         .mco2_from_pll2_p_ck(7.MHz())
-        .freeze(pwrcfg, &dp.SBS);
+        .freeze(&pwrcfg, &dp.SBS);
 
     // // Enable MCO2 output pin
     // let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);

examples/i2c.rs

@@ -27,7 +27,7 @@ fn main() -> ! {
     // Constrain and Freeze clock
     info!("Setup RCC...                  ");
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(100.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(100.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
 

examples/i2c_target.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     // Constrain and Freeze clock
     info!("Setup RCC...                  ");
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(100.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(100.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
 

examples/i2c_target_manual_ack.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     // Constrain and Freeze clock
     info!("Setup RCC...                  ");
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(100.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(100.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
 

examples/rcc.rs

@@ -24,7 +24,7 @@ fn main() -> ! {
     // Constrain and Freeze clock
     info!("Setup RCC...                  ");
     let rcc = dp.RCC.constrain();
-    let ccdr = rcc.sys_ck(250.MHz()).freeze(pwrcfg, &dp.SBS);
+    let ccdr = rcc.sys_ck(250.MHz()).freeze(&pwrcfg, &dp.SBS);
 
     info!("");
     info!("stm32h5xx-hal example - RCC");

examples/spi.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     let ccdr = rcc
         .sys_ck(192.MHz())
         .pll1_q_ck(64.MHz())
-        .freeze(pwrcfg, &dp.SBS);
+        .freeze(&pwrcfg, &dp.SBS);
 
     // Acquire the GPIOB peripheral. This also enables the clock for
     // GPIOB in the RCC register.

examples/spi_send_frames.rs

@@ -37,7 +37,7 @@ fn main() -> ! {
     let ccdr = rcc
         .sys_ck(192.MHz())
         .pll1_q_ck(64.MHz())
-        .freeze(pwrcfg, &dp.SBS);
+        .freeze(&pwrcfg, &dp.SBS);
 
     // Acquire the GPIOB peripheral. This also enables the clock for
     // GPIOB in the RCC register.