diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 5d9b215a..a9debc09 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,5 +1,6 @@ on: pull_request: + merge_group: name: Continuous integration diff --git a/.github/workflows/clippy.yml b/.github/workflows/clippy.yml index 49edc94d..48c5b653 100644 --- a/.github/workflows/clippy.yml +++ b/.github/workflows/clippy.yml @@ -2,6 +2,7 @@ on: push: branches: [ staging, trying, master ] pull_request: + merge_group: name: Clippy check diff --git a/.github/workflows/rustfmt.yml b/.github/workflows/rustfmt.yml index 7b350890..549e1000 100644 --- a/.github/workflows/rustfmt.yml +++ b/.github/workflows/rustfmt.yml @@ -2,6 +2,7 @@ on: push: branches: [ staging, trying, master ] pull_request: + merge_group: name: Code formatting check diff --git a/src/dac.rs b/src/dac.rs index 78f6a483..9571cd3a 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -12,6 +12,7 @@ use core::ops::Deref; use crate::gpio::{DefaultMode, PA4, PA5, PA6}; use crate::pac; use crate::rcc::{self, *}; +use crate::stm32::dac1::mcr::HFSEL; use crate::stm32::RCC; use embedded_hal::delay::DelayNs; @@ -260,15 +261,23 @@ impl_pin_for_dac!( (Dac4Ch1, Dac4Ch2) ); +pub fn hfsel(rcc: &Rcc) -> HFSEL { + match rcc.clocks.ahb_clk.to_MHz() { + 0..80 => pac::dac1::mcr::HFSEL::Disabled, + 80..160 => pac::dac1::mcr::HFSEL::More80mhz, + 160.. => pac::dac1::mcr::HFSEL::More160mhz, + } +} + impl DacCh { /// TODO: The DAC does not seem to work unless `calibrate_buffer` has been callen /// even when only using dac output internally - pub fn enable(self, _rcc: &mut Rcc) -> DacCh { + pub fn enable(self, rcc: &mut Rcc) -> DacCh { // We require rcc here just to ensure exclusive access to registers common to ch1 and ch2 let dac = unsafe { &(*DAC::ptr()) }; dac.mcr() - .modify(|_, w| unsafe { w.mode(CH).bits(MODE_BITS) }); + .modify(|_, w| unsafe { w.hfsel().variant(hfsel(rcc)).mode(CH).bits(MODE_BITS) }); dac.cr().modify(|_, w| w.en(CH).set_bit()); DacCh::new() @@ -277,13 +286,13 @@ impl DacCh DacCh { // We require rcc here just to ensure exclusive access to registers common to ch1 and ch2 let dac = unsafe { &(*DAC::ptr()) }; dac.mcr() - .modify(|_, w| unsafe { w.mode(CH).bits(MODE_BITS) }); + .modify(|_, w| unsafe { w.hfsel().variant(hfsel(rcc)).mode(CH).bits(MODE_BITS) }); dac.cr().modify(|_, w| unsafe { w.wave(CH).bits(config.mode); w.ten(CH).set_bit(); @@ -297,13 +306,13 @@ impl DacCh DacCh { // TODO: We require rcc here just to ensure exclusive access to registers common to ch1 and ch2 let dac = unsafe { &(*DAC::ptr()) }; dac.mcr() - .modify(|_, w| unsafe { w.mode(CH).bits(MODE_BITS) }); + .modify(|_, w| unsafe { w.hfsel().variant(hfsel(rcc)).mode(CH).bits(MODE_BITS) }); unsafe { dac.stmodr().modify(|_, w| {