arm64ec

Author: dpaoliello

crates/core_arch/src/aarch64/neon/mod.rs

@@ -2074,7 +2074,7 @@ pub unsafe fn vget_low_p64(a: poly64x2_t) -> poly64x1_t {
 #[target_feature(enable = "neon")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, IMM5 = 0))]
+#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, IMM5 = 0))]
 pub unsafe fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
     static_assert!(IMM5 == 0);
     simd_extract!(v, IMM5 as u32)
@@ -2085,7 +2085,7 @@ pub unsafe fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
 #[target_feature(enable = "neon")]
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, IMM5 = 0))]
+#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, IMM5 = 0))]
 pub unsafe fn vgetq_lane_f64<const IMM5: i32>(v: float64x2_t) -> f64 {
     static_assert_uimm_bits!(IMM5, 1);
     simd_extract!(v, IMM5 as u32)
@@ -3417,7 +3417,7 @@ pub unsafe fn vsm3tt1aq_u32<const IMM2: i32>(
     static_assert_uimm_bits!(IMM2, 2);
     #[allow(improper_ctypes)]
     extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt1a")]
+        #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt1a")]
         fn vsm3tt1aq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
     }
     vsm3tt1aq_u32_(a, b, c, IMM2 as i64)
@@ -3437,7 +3437,7 @@ pub unsafe fn vsm3tt1bq_u32<const IMM2: i32>(
     static_assert_uimm_bits!(IMM2, 2);
     #[allow(improper_ctypes)]
     extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt1b")]
+        #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt1b")]
         fn vsm3tt1bq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
     }
     vsm3tt1bq_u32_(a, b, c, IMM2 as i64)
@@ -3457,7 +3457,7 @@ pub unsafe fn vsm3tt2aq_u32<const IMM2: i32>(
     static_assert_uimm_bits!(IMM2, 2);
     #[allow(improper_ctypes)]
     extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt2a")]
+        #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt2a")]
         fn vsm3tt2aq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
     }
     vsm3tt2aq_u32_(a, b, c, IMM2 as i64)
@@ -3477,7 +3477,7 @@ pub unsafe fn vsm3tt2bq_u32<const IMM2: i32>(
     static_assert_uimm_bits!(IMM2, 2);
     #[allow(improper_ctypes)]
     extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sm3tt2b")]
+        #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3tt2b")]
         fn vsm3tt2bq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, imm2: i64) -> uint32x4_t;
     }
     vsm3tt2bq_u32_(a, b, c, IMM2 as i64)
@@ -3493,7 +3493,7 @@ pub unsafe fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64
     static_assert_uimm_bits!(IMM6, 6);
     #[allow(improper_ctypes)]
     extern "unadjusted" {
-        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.xar")]
+        #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.xar")]
         fn vxarq_u64_(a: uint64x2_t, b: uint64x2_t, n: i64) -> uint64x2_t;
     }
     vxarq_u64_(a, b, IMM6 as i64)

crates/core_arch/src/arm_shared/barrier/mod.rs

@@ -4,6 +4,7 @@
 #[cfg(not(any(
     // v8
     target_arch = "aarch64",
+    target_arch = "arm64ec",
     // v7
     target_feature = "v7",
     // v6-M
@@ -13,6 +14,7 @@ mod cp15;
 
 #[cfg(not(any(
     target_arch = "aarch64",
+    target_arch = "arm64ec",
     target_feature = "v7",
     target_feature = "mclass"
 )))]
@@ -22,6 +24,7 @@ pub use self::cp15::*;
 // Dedicated instructions
 #[cfg(any(
     target_arch = "aarch64",
+    target_arch = "arm64ec",
     target_feature = "v7",
     target_feature = "mclass"
 ))]
@@ -47,30 +50,32 @@ macro_rules! dmb_dsb {
 
 #[cfg(any(
     target_arch = "aarch64",
+    target_arch = "arm64ec",
     target_feature = "v7",
     target_feature = "mclass"
 ))]
 mod common;
 
 #[cfg(any(
     target_arch = "aarch64",
+    target_arch = "arm64ec",
     target_feature = "v7",
     target_feature = "mclass"
 ))]
 #[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
 pub use self::common::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec",target_feature = "v7",))]
 mod not_mclass;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7",))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7",))]
 #[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
 pub use self::not_mclass::*;
 
-#[cfg(target_arch = "aarch64")]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
 mod v8;
 
-#[cfg(target_arch = "aarch64")]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
 #[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
 pub use self::v8::*;
 
@@ -132,15 +137,15 @@ where
 }
 
 extern "unadjusted" {
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dmb")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.dmb")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dmb")]
     fn dmb(_: i32);
 
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.dsb")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.dsb")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.dsb")]
     fn dsb(_: i32);
 
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.isb")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.isb")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.isb")]
     fn isb(_: i32);
 }

crates/core_arch/src/arm_shared/crc.rs

@@ -1,26 +1,26 @@
 extern "unadjusted" {
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32b")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32b")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
     fn crc32b_(crc: u32, data: u32) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32h")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32h")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
     fn crc32h_(crc: u32, data: u32) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32w")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32w")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
     fn crc32w_(crc: u32, data: u32) -> u32;
 
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cb")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32cb")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
     fn crc32cb_(crc: u32, data: u32) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32ch")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32ch")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
     fn crc32ch_(crc: u32, data: u32) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cw")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32cw")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
     fn crc32cw_(crc: u32, data: u32) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32x")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32x")]
     fn crc32x_(crc: u32, data: u64) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cx")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crc32cx")]
     fn crc32cx_(crc: u32, data: u64) -> u32;
 }
 
@@ -104,7 +104,7 @@ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
 #[inline]
 #[target_feature(enable = "crc")]
-#[cfg(target_arch = "aarch64")]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(crc32x))]
 #[unstable(feature = "stdarch_arm_crc32", issue = "117215")]
 pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
@@ -133,7 +133,7 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
 /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)
 #[inline]
 #[target_feature(enable = "crc")]
-#[cfg(target_arch = "aarch64")]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
 #[cfg_attr(test, assert_instr(crc32cx))]
 #[unstable(feature = "stdarch_arm_crc32", issue = "117215")]
 pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {

crates/core_arch/src/arm_shared/crypto.rs

@@ -2,48 +2,48 @@ use crate::core_arch::arm_shared::{uint32x4_t, uint8x16_t};
 
 #[allow(improper_ctypes)]
 extern "unadjusted" {
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aese")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aese")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
     fn vaeseq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesd")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aesd")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
     fn vaesdq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesmc")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aesmc")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
     fn vaesmcq_u8_(data: uint8x16_t) -> uint8x16_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.aesimc")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.aesimc")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
     fn vaesimcq_u8_(data: uint8x16_t) -> uint8x16_t;
 
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1h")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1h")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
     fn vsha1h_u32_(hash_e: u32) -> u32;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1su0")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1su0")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
     fn vsha1su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1su1")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1su1")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
     fn vsha1su1q_u32_(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1c")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1c")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
     fn vsha1cq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1p")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1p")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
     fn vsha1pq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha1m")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha1m")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
     fn vsha1mq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
 
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256h")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256h")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
     fn vsha256hq_u32_(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256h2")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256h2")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
     fn vsha256h2q_u32_(hash_efgh: uint32x4_t, hash_abcd: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256su0")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256su0")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
     fn vsha256su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crypto.sha256su1")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha256su1")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
     fn vsha256su1q_u32_(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
 }

crates/core_arch/src/arm_shared/hints.rs

@@ -9,7 +9,7 @@
 /// low-power state until one of a number of asynchronous events occurs.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
 #[inline(always)]
 #[unstable(feature = "stdarch_arm_hints", issue = "117218")]
 pub unsafe fn __wfi() {
@@ -23,7 +23,7 @@ pub unsafe fn __wfi() {
 /// another processor.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
 #[inline(always)]
 #[unstable(feature = "stdarch_arm_hints", issue = "117218")]
 pub unsafe fn __wfe() {
@@ -36,7 +36,7 @@ pub unsafe fn __wfe() {
 /// system. It is a NOP on a uniprocessor system.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M, 7-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
 #[inline(always)]
 #[unstable(feature = "stdarch_arm_hints", issue = "117218")]
 pub unsafe fn __sev() {
@@ -52,6 +52,7 @@ pub unsafe fn __sev() {
 #[cfg(any(
     target_feature = "v8", // 32-bit ARMv8
     target_arch = "aarch64", // AArch64
+    target_arch = "arm64ec", // Arm64EC
     doc,
 ))]
 #[inline(always)]
@@ -67,7 +68,7 @@ pub unsafe fn __sevl() {
 /// improve overall system performance.
 // Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M
 // LLVM says "instruction requires: armv6k"
-#[cfg(any(target_feature = "v6", target_arch = "aarch64", doc))]
+#[cfg(any(target_feature = "v6", target_arch = "aarch64", target_arch = "arm64ec", doc))]
 #[inline(always)]
 #[unstable(feature = "stdarch_arm_hints", issue = "117218")]
 pub unsafe fn __yield() {
@@ -80,14 +81,16 @@ pub unsafe fn __yield() {
 /// those that do, it is unspecified whether this intrinsic generates it or
 /// another instruction. It is not guaranteed that inserting this instruction
 /// will increase execution time.
+// Inline ASM is not support on ARM64EC yet.
+#[cfg(not(target_arch = "arm64ec"))]
 #[inline(always)]
 #[unstable(feature = "stdarch_arm_hints", issue = "117218")]
 pub unsafe fn __nop() {
     crate::arch::asm!("nop", options(nomem, nostack, preserves_flags));
 }
 
 extern "unadjusted" {
-    #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.hint")]
+    #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.hint")]
     #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.hint")]
     fn hint(_: i32);
 }

crates/core_arch/src/arm_shared/mod.rs

@@ -66,11 +66,11 @@ pub use crc::*;
 
 // NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
 #[cfg(target_endian = "little")]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
 mod crypto;
 // NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
 #[cfg(target_endian = "little")]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
 #[cfg_attr(
     target_arch = "arm",
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
@@ -83,10 +83,10 @@ pub use self::crypto::*;
 
 // NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
 #[cfg(target_endian = "little")]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
 pub(crate) mod neon;
 #[cfg(target_endian = "little")]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "neon_intrinsics", since = "1.59.0")
@@ -98,7 +98,7 @@ pub(crate) mod neon;
 pub use self::neon::*;
 
 #[cfg(test)]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_feature = "v7", doc))]
 pub(crate) mod test_support;
 
 mod sealed {

crates/core_arch/src/arm_shared/neon/load_tests.rs

@@ -7,7 +7,7 @@ use super::*;
 #[cfg(target_arch = "arm")]
 use crate::core_arch::arm::*;
 
-#[cfg(target_arch = "aarch64")]
+#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
 use crate::core_arch::aarch64::*;
 
 use crate::core_arch::simd::*;