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antoyo merged 1 commit into from
Dec 4, 2025
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Regenerate intrinsics #814

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123 changes: 99 additions & 24 deletions src/intrinsic/archs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -70,10 +70,6 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"sve.sm4e" => "__builtin_sve_svsm4e_u32",
"sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32",
"sve.wrffr" => "__builtin_sve_svwrffr",
"tcancel" => "__builtin_arm_tcancel",
"tcommit" => "__builtin_arm_tcommit",
"tstart" => "__builtin_arm_tstart",
"ttest" => "__builtin_arm_ttest",
_ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
}
}
Expand Down Expand Up @@ -1632,6 +1628,14 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"V6.vabs.f8.128B" => "__builtin_HEXAGON_V6_vabs_f8_128B",
"V6.vabs.hf" => "__builtin_HEXAGON_V6_vabs_hf",
"V6.vabs.hf.128B" => "__builtin_HEXAGON_V6_vabs_hf_128B",
"V6.vabs.qf16.hf" => "__builtin_HEXAGON_V6_vabs_qf16_hf",
"V6.vabs.qf16.hf.128B" => "__builtin_HEXAGON_V6_vabs_qf16_hf_128B",
"V6.vabs.qf16.qf16" => "__builtin_HEXAGON_V6_vabs_qf16_qf16",
"V6.vabs.qf16.qf16.128B" => "__builtin_HEXAGON_V6_vabs_qf16_qf16_128B",
"V6.vabs.qf32.qf32" => "__builtin_HEXAGON_V6_vabs_qf32_qf32",
"V6.vabs.qf32.qf32.128B" => "__builtin_HEXAGON_V6_vabs_qf32_qf32_128B",
"V6.vabs.qf32.sf" => "__builtin_HEXAGON_V6_vabs_qf32_sf",
"V6.vabs.qf32.sf.128B" => "__builtin_HEXAGON_V6_vabs_qf32_sf_128B",
"V6.vabs.sf" => "__builtin_HEXAGON_V6_vabs_sf",
"V6.vabs.sf.128B" => "__builtin_HEXAGON_V6_vabs_sf_128B",
"V6.vabsb" => "__builtin_HEXAGON_V6_vabsb",
Expand Down Expand Up @@ -1744,6 +1748,8 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"V6.vaddwsat.128B" => "__builtin_HEXAGON_V6_vaddwsat_128B",
"V6.vaddwsat.dv" => "__builtin_HEXAGON_V6_vaddwsat_dv",
"V6.vaddwsat.dv.128B" => "__builtin_HEXAGON_V6_vaddwsat_dv_128B",
"V6.valign4" => "__builtin_HEXAGON_V6_valign4",
"V6.valign4.128B" => "__builtin_HEXAGON_V6_valign4_128B",
"V6.valignb" => "__builtin_HEXAGON_V6_valignb",
"V6.valignb.128B" => "__builtin_HEXAGON_V6_valignb_128B",
"V6.valignbi" => "__builtin_HEXAGON_V6_valignbi",
Expand Down Expand Up @@ -1862,14 +1868,30 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B",
"V6.vcombine" => "__builtin_HEXAGON_V6_vcombine",
"V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B",
"V6.vconv.bf.qf32" => "__builtin_HEXAGON_V6_vconv_bf_qf32",
"V6.vconv.bf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_bf_qf32_128B",
"V6.vconv.f8.qf16" => "__builtin_HEXAGON_V6_vconv_f8_qf16",
"V6.vconv.f8.qf16.128B" => "__builtin_HEXAGON_V6_vconv_f8_qf16_128B",
"V6.vconv.h.hf" => "__builtin_HEXAGON_V6_vconv_h_hf",
"V6.vconv.h.hf.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_128B",
"V6.vconv.h.hf.rnd" => "__builtin_HEXAGON_V6_vconv_h_hf_rnd",
"V6.vconv.h.hf.rnd.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_rnd_128B",
"V6.vconv.hf.h" => "__builtin_HEXAGON_V6_vconv_hf_h",
"V6.vconv.hf.h.128B" => "__builtin_HEXAGON_V6_vconv_hf_h_128B",
"V6.vconv.hf.qf16" => "__builtin_HEXAGON_V6_vconv_hf_qf16",
"V6.vconv.hf.qf16.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf16_128B",
"V6.vconv.hf.qf32" => "__builtin_HEXAGON_V6_vconv_hf_qf32",
"V6.vconv.hf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf32_128B",
"V6.vconv.qf16.f8" => "__builtin_HEXAGON_V6_vconv_qf16_f8",
"V6.vconv.qf16.f8.128B" => "__builtin_HEXAGON_V6_vconv_qf16_f8_128B",
"V6.vconv.qf16.hf" => "__builtin_HEXAGON_V6_vconv_qf16_hf",
"V6.vconv.qf16.hf.128B" => "__builtin_HEXAGON_V6_vconv_qf16_hf_128B",
"V6.vconv.qf16.qf16" => "__builtin_HEXAGON_V6_vconv_qf16_qf16",
"V6.vconv.qf16.qf16.128B" => "__builtin_HEXAGON_V6_vconv_qf16_qf16_128B",
"V6.vconv.qf32.qf32" => "__builtin_HEXAGON_V6_vconv_qf32_qf32",
"V6.vconv.qf32.qf32.128B" => "__builtin_HEXAGON_V6_vconv_qf32_qf32_128B",
"V6.vconv.qf32.sf" => "__builtin_HEXAGON_V6_vconv_qf32_sf",
"V6.vconv.qf32.sf.128B" => "__builtin_HEXAGON_V6_vconv_qf32_sf_128B",
"V6.vconv.sf.qf32" => "__builtin_HEXAGON_V6_vconv_sf_qf32",
"V6.vconv.sf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_sf_qf32_128B",
"V6.vconv.sf.w" => "__builtin_HEXAGON_V6_vconv_sf_w",
Expand Down Expand Up @@ -1984,6 +2006,22 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"V6.veqh.or.128B" => "__builtin_HEXAGON_V6_veqh_or_128B",
"V6.veqh.xor" => "__builtin_HEXAGON_V6_veqh_xor",
"V6.veqh.xor.128B" => "__builtin_HEXAGON_V6_veqh_xor_128B",
"V6.veqhf" => "__builtin_HEXAGON_V6_veqhf",
"V6.veqhf.128B" => "__builtin_HEXAGON_V6_veqhf_128B",
"V6.veqhf.and" => "__builtin_HEXAGON_V6_veqhf_and",
"V6.veqhf.and.128B" => "__builtin_HEXAGON_V6_veqhf_and_128B",
"V6.veqhf.or" => "__builtin_HEXAGON_V6_veqhf_or",
"V6.veqhf.or.128B" => "__builtin_HEXAGON_V6_veqhf_or_128B",
"V6.veqhf.xor" => "__builtin_HEXAGON_V6_veqhf_xor",
"V6.veqhf.xor.128B" => "__builtin_HEXAGON_V6_veqhf_xor_128B",
"V6.veqsf" => "__builtin_HEXAGON_V6_veqsf",
"V6.veqsf.128B" => "__builtin_HEXAGON_V6_veqsf_128B",
"V6.veqsf.and" => "__builtin_HEXAGON_V6_veqsf_and",
"V6.veqsf.and.128B" => "__builtin_HEXAGON_V6_veqsf_and_128B",
"V6.veqsf.or" => "__builtin_HEXAGON_V6_veqsf_or",
"V6.veqsf.or.128B" => "__builtin_HEXAGON_V6_veqsf_or_128B",
"V6.veqsf.xor" => "__builtin_HEXAGON_V6_veqsf_xor",
"V6.veqsf.xor.128B" => "__builtin_HEXAGON_V6_veqsf_xor_128B",
"V6.veqw" => "__builtin_HEXAGON_V6_veqw",
"V6.veqw.128B" => "__builtin_HEXAGON_V6_veqw_128B",
"V6.veqw.and" => "__builtin_HEXAGON_V6_veqw_and",
Expand Down Expand Up @@ -2096,6 +2134,14 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"V6.vgtw.or.128B" => "__builtin_HEXAGON_V6_vgtw_or_128B",
"V6.vgtw.xor" => "__builtin_HEXAGON_V6_vgtw_xor",
"V6.vgtw.xor.128B" => "__builtin_HEXAGON_V6_vgtw_xor_128B",
"V6.vilog2.hf" => "__builtin_HEXAGON_V6_vilog2_hf",
"V6.vilog2.hf.128B" => "__builtin_HEXAGON_V6_vilog2_hf_128B",
"V6.vilog2.qf16" => "__builtin_HEXAGON_V6_vilog2_qf16",
"V6.vilog2.qf16.128B" => "__builtin_HEXAGON_V6_vilog2_qf16_128B",
"V6.vilog2.qf32" => "__builtin_HEXAGON_V6_vilog2_qf32",
"V6.vilog2.qf32.128B" => "__builtin_HEXAGON_V6_vilog2_qf32_128B",
"V6.vilog2.sf" => "__builtin_HEXAGON_V6_vilog2_sf",
"V6.vilog2.sf.128B" => "__builtin_HEXAGON_V6_vilog2_sf_128B",
"V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr",
"V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B",
"V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb",
Expand Down Expand Up @@ -2350,6 +2396,14 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"V6.vnavgub.128B" => "__builtin_HEXAGON_V6_vnavgub_128B",
"V6.vnavgw" => "__builtin_HEXAGON_V6_vnavgw",
"V6.vnavgw.128B" => "__builtin_HEXAGON_V6_vnavgw_128B",
"V6.vneg.qf16.hf" => "__builtin_HEXAGON_V6_vneg_qf16_hf",
"V6.vneg.qf16.hf.128B" => "__builtin_HEXAGON_V6_vneg_qf16_hf_128B",
"V6.vneg.qf16.qf16" => "__builtin_HEXAGON_V6_vneg_qf16_qf16",
"V6.vneg.qf16.qf16.128B" => "__builtin_HEXAGON_V6_vneg_qf16_qf16_128B",
"V6.vneg.qf32.qf32" => "__builtin_HEXAGON_V6_vneg_qf32_qf32",
"V6.vneg.qf32.qf32.128B" => "__builtin_HEXAGON_V6_vneg_qf32_qf32_128B",
"V6.vneg.qf32.sf" => "__builtin_HEXAGON_V6_vneg_qf32_sf",
"V6.vneg.qf32.sf.128B" => "__builtin_HEXAGON_V6_vneg_qf32_sf_128B",
"V6.vnormamth" => "__builtin_HEXAGON_V6_vnormamth",
"V6.vnormamth.128B" => "__builtin_HEXAGON_V6_vnormamth_128B",
"V6.vnormamtw" => "__builtin_HEXAGON_V6_vnormamtw",
Expand Down Expand Up @@ -2684,6 +2738,24 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"iocsrwr.d" => "__builtin_loongarch_iocsrwr_d",
"iocsrwr.h" => "__builtin_loongarch_iocsrwr_h",
"iocsrwr.w" => "__builtin_loongarch_iocsrwr_w",
"lasx.cast.128" => "__builtin_lasx_cast_128",
"lasx.cast.128.d" => "__builtin_lasx_cast_128_d",
"lasx.cast.128.s" => "__builtin_lasx_cast_128_s",
"lasx.concat.128" => "__builtin_lasx_concat_128",
"lasx.concat.128.d" => "__builtin_lasx_concat_128_d",
"lasx.concat.128.s" => "__builtin_lasx_concat_128_s",
"lasx.extract.128.hi" => "__builtin_lasx_extract_128_hi",
"lasx.extract.128.hi.d" => "__builtin_lasx_extract_128_hi_d",
"lasx.extract.128.hi.s" => "__builtin_lasx_extract_128_hi_s",
"lasx.extract.128.lo" => "__builtin_lasx_extract_128_lo",
"lasx.extract.128.lo.d" => "__builtin_lasx_extract_128_lo_d",
"lasx.extract.128.lo.s" => "__builtin_lasx_extract_128_lo_s",
"lasx.insert.128.hi" => "__builtin_lasx_insert_128_hi",
"lasx.insert.128.hi.d" => "__builtin_lasx_insert_128_hi_d",
"lasx.insert.128.hi.s" => "__builtin_lasx_insert_128_hi_s",
"lasx.insert.128.lo" => "__builtin_lasx_insert_128_lo",
"lasx.insert.128.lo.d" => "__builtin_lasx_insert_128_lo_d",
"lasx.insert.128.lo.s" => "__builtin_lasx_insert_128_lo_s",
"lasx.vext2xv.d.b" => "__builtin_lasx_vext2xv_d_b",
"lasx.vext2xv.d.h" => "__builtin_lasx_vext2xv_d_h",
"lasx.vext2xv.d.w" => "__builtin_lasx_vext2xv_d_w",
Expand Down Expand Up @@ -4950,8 +5022,20 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"f16x2.to.e5m2x2.rn.relu" => "__nvvm_f16x2_to_e5m2x2_rn_relu",
"f2bf16.rn" => "__nvvm_f2bf16_rn",
"f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu",
"f2bf16.rn.relu.satfinite" => "__nvvm_f2bf16_rn_relu_satfinite",
"f2bf16.rn.satfinite" => "__nvvm_f2bf16_rn_satfinite",
"f2bf16.rz" => "__nvvm_f2bf16_rz",
"f2bf16.rz.relu" => "__nvvm_f2bf16_rz_relu",
"f2bf16.rz.relu.satfinite" => "__nvvm_f2bf16_rz_relu_satfinite",
"f2bf16.rz.satfinite" => "__nvvm_f2bf16_rz_satfinite",
"f2f16.rn" => "__nvvm_f2f16_rn",
"f2f16.rn.relu" => "__nvvm_f2f16_rn_relu",
"f2f16.rn.relu.satfinite" => "__nvvm_f2f16_rn_relu_satfinite",
"f2f16.rn.satfinite" => "__nvvm_f2f16_rn_satfinite",
"f2f16.rz" => "__nvvm_f2f16_rz",
"f2f16.rz.relu" => "__nvvm_f2f16_rz_relu",
"f2f16.rz.relu.satfinite" => "__nvvm_f2f16_rz_relu_satfinite",
"f2f16.rz.satfinite" => "__nvvm_f2f16_rz_satfinite",
"f2h.rn" => "__nvvm_f2h_rn",
"f2h.rn.ftz" => "__nvvm_f2h_rn_ftz",
"f2i.rm" => "__nvvm_f2i_rm",
Expand Down Expand Up @@ -5035,20 +5119,28 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"ff.to.ue8m0x2.rz.satfinite" => "__nvvm_ff_to_ue8m0x2_rz_satfinite",
"ff2bf16x2.rn" => "__nvvm_ff2bf16x2_rn",
"ff2bf16x2.rn.relu" => "__nvvm_ff2bf16x2_rn_relu",
"ff2bf16x2.rn.relu.satfinite" => "__nvvm_ff2bf16x2_rn_relu_satfinite",
"ff2bf16x2.rn.satfinite" => "__nvvm_ff2bf16x2_rn_satfinite",
"ff2bf16x2.rs" => "__nvvm_ff2bf16x2_rs",
"ff2bf16x2.rs.relu" => "__nvvm_ff2bf16x2_rs_relu",
"ff2bf16x2.rs.relu.satfinite" => "__nvvm_ff2bf16x2_rs_relu_satfinite",
"ff2bf16x2.rs.satfinite" => "__nvvm_ff2bf16x2_rs_satfinite",
"ff2bf16x2.rz" => "__nvvm_ff2bf16x2_rz",
"ff2bf16x2.rz.relu" => "__nvvm_ff2bf16x2_rz_relu",
"ff2bf16x2.rz.relu.satfinite" => "__nvvm_ff2bf16x2_rz_relu_satfinite",
"ff2bf16x2.rz.satfinite" => "__nvvm_ff2bf16x2_rz_satfinite",
"ff2f16x2.rn" => "__nvvm_ff2f16x2_rn",
"ff2f16x2.rn.relu" => "__nvvm_ff2f16x2_rn_relu",
"ff2f16x2.rn.relu.satfinite" => "__nvvm_ff2f16x2_rn_relu_satfinite",
"ff2f16x2.rn.satfinite" => "__nvvm_ff2f16x2_rn_satfinite",
"ff2f16x2.rs" => "__nvvm_ff2f16x2_rs",
"ff2f16x2.rs.relu" => "__nvvm_ff2f16x2_rs_relu",
"ff2f16x2.rs.relu.satfinite" => "__nvvm_ff2f16x2_rs_relu_satfinite",
"ff2f16x2.rs.satfinite" => "__nvvm_ff2f16x2_rs_satfinite",
"ff2f16x2.rz" => "__nvvm_ff2f16x2_rz",
"ff2f16x2.rz.relu" => "__nvvm_ff2f16x2_rz_relu",
"ff2f16x2.rz.relu.satfinite" => "__nvvm_ff2f16x2_rz_relu_satfinite",
"ff2f16x2.rz.satfinite" => "__nvvm_ff2f16x2_rz_satfinite",
"floor.d" => "__nvvm_floor_d",
"floor.f" => "__nvvm_floor_f",
"floor.ftz.f" => "__nvvm_floor_ftz_f",
Expand Down Expand Up @@ -5942,6 +6034,8 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"altivec.vupklsb" => "__builtin_altivec_vupklsb",
"altivec.vupklsh" => "__builtin_altivec_vupklsh",
"altivec.vupklsw" => "__builtin_altivec_vupklsw",
"amo.ldat" => "__builtin_amo_ldat",
"amo.lwat" => "__builtin_amo_lwat",
"bcdadd" => "__builtin_ppc_bcdadd",
"bcdadd.p" => "__builtin_ppc_bcdadd_p",
"bcdcopysign" => "__builtin_ppc_bcdcopysign",
Expand Down Expand Up @@ -6202,6 +6296,7 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"vsx.xvminsp" => "__builtin_vsx_xvminsp",
"vsx.xvredp" => "__builtin_vsx_xvredp",
"vsx.xvresp" => "__builtin_vsx_xvresp",
"vsx.xvrlw" => "__builtin_vsx_xvrlw",
"vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp",
"vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp",
"vsx.xvtdivdp" => "__builtin_vsx_xvtdivdp",
Expand Down Expand Up @@ -10158,24 +10253,16 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"stui" => "__builtin_ia32_stui",
"subborrow.u32" => "__builtin_ia32_subborrow_u32",
"subborrow.u64" => "__builtin_ia32_subborrow_u64",
"t2rpntlvwz0" => "__builtin_ia32_t2rpntlvwz0",
"t2rpntlvwz0rs" => "__builtin_ia32_t2rpntlvwz0rs",
"t2rpntlvwz0rst1" => "__builtin_ia32_t2rpntlvwz0rst1",
"t2rpntlvwz0t1" => "__builtin_ia32_t2rpntlvwz0t1",
"t2rpntlvwz1" => "__builtin_ia32_t2rpntlvwz1",
"t2rpntlvwz1rs" => "__builtin_ia32_t2rpntlvwz1rs",
"t2rpntlvwz1rst1" => "__builtin_ia32_t2rpntlvwz1rst1",
"t2rpntlvwz1t1" => "__builtin_ia32_t2rpntlvwz1t1",
"tbm.bextri.u32" => "__builtin_ia32_bextri_u32",
"tbm.bextri.u64" => "__builtin_ia32_bextri_u64",
"tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps",
"tcmmimfp16ps.internal" => "__builtin_ia32_tcmmimfp16ps_internal",
"tcmmrlfp16ps" => "__builtin_ia32_tcmmrlfp16ps",
"tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal",
"tconjtcmmimfp16ps" => "__builtin_ia32_tconjtcmmimfp16ps",
"tconjtcmmimfp16ps.internal" => "__builtin_ia32_tconjtcmmimfp16ps_internal",
"tconjtfp16" => "__builtin_ia32_tconjtfp16",
"tconjtfp16.internal" => "__builtin_ia32_tconjtfp16_internal",
"tcvtrowd2ps" => "__builtin_ia32_tcvtrowd2ps",
"tcvtrowd2ps.internal" => "__builtin_ia32_tcvtrowd2ps_internal",
"tcvtrowps2bf16h" => "__builtin_ia32_tcvtrowps2bf16h",
Expand Down Expand Up @@ -10225,18 +10312,6 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
"tmmultf32ps" => "__builtin_ia32_tmmultf32ps",
"tmmultf32ps.internal" => "__builtin_ia32_tmmultf32ps_internal",
"tpause" => "__builtin_ia32_tpause",
"ttcmmimfp16ps" => "__builtin_ia32_ttcmmimfp16ps",
"ttcmmimfp16ps.internal" => "__builtin_ia32_ttcmmimfp16ps_internal",
"ttcmmrlfp16ps" => "__builtin_ia32_ttcmmrlfp16ps",
"ttcmmrlfp16ps.internal" => "__builtin_ia32_ttcmmrlfp16ps_internal",
"ttdpbf16ps" => "__builtin_ia32_ttdpbf16ps",
"ttdpbf16ps.internal" => "__builtin_ia32_ttdpbf16ps_internal",
"ttdpfp16ps" => "__builtin_ia32_ttdpfp16ps",
"ttdpfp16ps.internal" => "__builtin_ia32_ttdpfp16ps_internal",
"ttmmultf32ps" => "__builtin_ia32_ttmmultf32ps",
"ttmmultf32ps.internal" => "__builtin_ia32_ttmmultf32ps_internal",
"ttransposed" => "__builtin_ia32_ttransposed",
"ttransposed.internal" => "__builtin_ia32_ttransposed_internal",
"umonitor" => "__builtin_ia32_umonitor",
"umwait" => "__builtin_ia32_umwait",
"urdmsr" => "__builtin_ia32_urdmsr",
Expand Down