@@ -322,20 +322,21 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
322322 }
323323 assert_eq!( a. layout( ) , b. layout( ) ) ;
324324 assert_eq!( a. layout( ) , c. layout( ) ) ;
325- let layout = a . layout( ) ;
325+ assert_eq! ( a . layout( ) , ret . layout( ) ) ;
326326
327- let ( lane_count, _lane_ty) = layout. ty. simd_size_and_type( fx. tcx) ;
328- let ( ret_lane_count, ret_lane_ty) = ret. layout( ) . ty. simd_size_and_type( fx. tcx) ;
329- assert_eq!( lane_count, ret_lane_count) ;
330- let ret_lane_layout = fx. layout_of( ret_lane_ty) ;
327+ let layout = a. layout( ) ;
328+ let ( lane_count, lane_ty) = layout. ty. simd_size_and_type( fx. tcx) ;
331329
332330 for lane in 0 ..lane_count {
333- let a_lane = a. value_lane( fx, lane) . load_scalar ( fx ) ;
334- let b_lane = b. value_lane( fx, lane) . load_scalar ( fx ) ;
335- let c_lane = c. value_lane( fx, lane) . load_scalar ( fx ) ;
331+ let a_lane = a. value_lane( fx, lane) ;
332+ let b_lane = b. value_lane( fx, lane) ;
333+ let c_lane = c. value_lane( fx, lane) ;
336334
337- let mul_lane = fx. bcx. ins( ) . fmul( a_lane, b_lane) ;
338- let res_lane = CValue :: by_val( fx. bcx. ins( ) . fadd( mul_lane, c_lane) , ret_lane_layout) ;
335+ let res_lane = match lane_ty. kind( ) {
336+ ty:: Float ( FloatTy :: F32 ) => fx. easy_call( "fmaf" , & [ a_lane, b_lane, c_lane] , lane_ty) ,
337+ ty:: Float ( FloatTy :: F64 ) => fx. easy_call( "fma" , & [ a_lane, b_lane, c_lane] , lane_ty) ,
338+ _ => unreachable!( ) ,
339+ } ;
339340
340341 ret. place_lane( fx, lane) . write_cvalue( fx, res_lane) ;
341342 }
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