From f32d1828bd65fefa6271d88986222b240d1d304e Mon Sep 17 00:00:00 2001
From: CUB3D <callumthom11@gmail.com>
Date: Mon, 27 Oct 2025 09:39:31 +0000
Subject: [PATCH] Add MDSCR_EL1

---
 src/registers.rs           |   2 +
 src/registers/mdscr_el1.rs | 137 +++++++++++++++++++++++++++++++++++++
 2 files changed, 139 insertions(+)
 create mode 100644 src/registers/mdscr_el1.rs

diff --git a/src/registers.rs b/src/registers.rs
index 97f8622..078ffd1 100644
--- a/src/registers.rs
+++ b/src/registers.rs
@@ -107,6 +107,7 @@ mod lr;
 mod mair_el1;
 mod mair_el2;
 mod mdccsr_el0;
+mod mdscr_el1;
 mod midr_el1;
 mod mpidr_el1;
 mod oslar_el1;
@@ -245,6 +246,7 @@ pub use lr::LR;
 pub use mair_el1::MAIR_EL1;
 pub use mair_el2::MAIR_EL2;
 pub use mdccsr_el0::MDCCSR_EL0;
+pub use mdscr_el1::MDSCR_EL1;
 pub use midr_el1::MIDR_EL1;
 pub use mpidr_el1::MPIDR_EL1;
 pub use oslar_el1::OSLAR_EL1;
diff --git a/src/registers/mdscr_el1.rs b/src/registers/mdscr_el1.rs
new file mode 100644
index 0000000..c8f7054
--- /dev/null
+++ b/src/registers/mdscr_el1.rs
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Monitor Debug System Control Register - EL1
+//!
+//! Main control register for debug functions.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub MDSCR_EL1 [
+        /// Software step control bit.
+        ///
+        /// Enables execution from MDSTEPOP_EL1
+        EnSTEPOP OFFSET(50) NUMBITS(1) [],
+
+        /// Extended Halting Breakpoint and Watchpoint Enable.
+        EHBWE OFFSET(35) NUMBITS(1) [],
+
+        /// Enable use of System PMU registers.
+        EnSPM OFFSET(34) NUMBITS(1) [
+            TrapSystemPMUAccess = 0,
+            AllocSystemPMUAccess = 1,
+        ],
+
+        /// Trap Trace Accesses.
+        TTA OFFSET(33) NUMBITS(1) [],
+
+        /// Extended Monitor Breakpoint and Watchpoint Enable.
+        EMBWE OFFSET(32) NUMBITS(1) [],
+
+        /// Trace Filter Override.
+        TFO OFFSET(31) NUMBITS(1) [],
+
+        /// RXfull.
+        ///
+        /// Used to save and restore the value of EDSCR.RXfull.
+        RXfull OFFSET(30) NUMBITS(1) [],
+
+        /// TXfull.
+        ///
+        /// Used to save and restore the value of EDSCR.TXfull.
+        TXfull OFFSET(29) NUMBITS(1) [],
+
+        /// RXO.
+        ///
+        /// Used to save and restore the value of EDSCR.RXO.
+        RXO OFFSET(27) NUMBITS(1) [],
+
+        /// TXU.
+        ///
+        /// Used to save and restore the value of EDSCR.TXU.
+        TXU OFFSET(26) NUMBITS(1) [],
+
+        /// INTdis.
+        ///
+        /// Used to save and restore the value of EDSCR.INTdis.
+        INTdis OFFSET(22) NUMBITS(2) [],
+
+        /// TDA.
+        ///
+        /// Used to save and restore the value of EDSCR.TDA.
+        TDA OFFSET(21) NUMBITS(1) [],
+
+        /// SC2.
+        ///
+        /// Requires FEAT_PCSRv8, FEAT_VHE to be implemented and FEAT_PCRv8p2 to not be
+        /// implemented.
+        ///
+        /// Used to save and restore the value of EDSCR.SC2.
+        SC2 OFFSET(19) NUMBITS(1) [],
+
+        /// Monitor Debug Events.
+        ///
+        /// Enables Breakpoint, Watchpoint and Vector Catch exceptions.
+        MDE OFFSET(15) NUMBITS(1) [],
+
+        /// HDE.
+        ///
+        /// Used to save and restore the value of EDSCR.HDE.
+        HDE OFFSET(14) NUMBITS(1) [],
+
+        /// Local (kernel) debug enable.
+        ///
+        /// Enables Debug Exceptions within EL_D when using AArch64
+        /// RES0 if EL_D is AArch32
+        KDE OFFSET(13) NUMBITS(1) [
+            OnlyBreakpointInstructionsEnabled = 0,
+            AllDebugExceptionsEnabled = 1,
+        ],
+
+        /// Trap DCC register access.
+        ///
+        /// Traps access to the Debug Communication Channel (DCC) registers from EL0 to higher
+        /// exception level.
+        TDCC OFFSET(12) NUMBITS(1) [],
+
+        /// ERR.
+        ///
+        /// Used to save and restore the value of EDSCR.ERR.
+        ERR OFFSET(6) NUMBITS(1) [],
+
+        /// Software step.
+        ///
+        /// Enable software step if EL_D is using AArch64
+        /// RES0 if EL_D is using AArch32
+        SS OFFSET(0) NUMBITS(1) [
+            SoftwareStepDisabled = 0,
+            SoftwareStepEnabled = 1,
+        ],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = MDSCR_EL1::Register;
+
+    sys_coproc_read_raw!(u64, "MDSCR_EL1", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = MDSCR_EL1::Register;
+
+    sys_coproc_write_raw!(u64, "MDSCR_EL1", "x");
+}
+
+pub const MDSCR_EL1: Reg = Reg {};