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Merge branch 'master' into rt/ace
2 parents 151cb48 + 251022d commit 8659446

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-37
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2 files changed

+68
-37
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‎src/axi_burst_unwrap.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -101,9 +101,9 @@ module axi_burst_unwrap #(
101101
// ATOPs are not supported.
102102
if (atop != '0) return 1'b0;
103103
// The AXI Spec (A3.4.1) only allows splitting non-modifiable transactions ..
104-
if (!axi_pkg::modifiable(cache)) begin
105-
// .. if they are INCR bursts and longer than 16 beats.
106-
return (burst == axi_pkg::BURST_INCR) & (len > 16);
104+
// ... but this module only splits WRAP bursts, so ignore all others
105+
if (!axi_pkg::modifiable(cache) && (burst == axi_pkg::BURST_WRAP)) begin
106+
return 1'b0;
107107
end
108108
// All other transactions are supported.
109109
return 1'b1;

‎src/axi_dw_downsizer.sv‎

Lines changed: 65 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -406,13 +406,16 @@ module axi_dw_downsizer #(
406406

407407
case (r_req_d.ar.burst)
408408
axi_pkg::BURST_INCR : begin
409+
automatic addr_t size_mask;
410+
automatic addr_t conv_ratio;
411+
automatic addr_t align_adj;
409412
// Evaluate downsize ratio
410-
automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ;
411-
automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
413+
size_mask = (1 << r_req_d.ar.size) - 1 ;
414+
conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
412415

413416
// Evaluate output burst length
414-
automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
415-
r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ;
417+
align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
418+
r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ;
416419

417420
if (conv_ratio != 1) begin
418421
r_req_d.ar.size = AxiMstPortMaxSize;
@@ -430,13 +433,16 @@ module axi_dw_downsizer #(
430433
axi_pkg::BURST_FIXED: begin
431434
// Single transaction
432435
if (r_req_d.ar.len == '0) begin
436+
automatic addr_t size_mask;
437+
automatic addr_t conv_ratio;
438+
automatic addr_t align_adj;
433439
// Evaluate downsize ratio
434-
automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ;
435-
automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
440+
size_mask = (1 << r_req_d.ar.size) - 1 ;
441+
conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
436442

437443
// Evaluate output burst length
438-
automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
439-
r_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0;
444+
align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
445+
r_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0 ;
440446

441447
if (conv_ratio != 1) begin
442448
r_state_d = R_INCR_DOWNSIZE ;
@@ -455,6 +461,8 @@ module axi_dw_downsizer #(
455461
r_state_d = R_PASSTHROUGH;
456462
r_req_d.ar_throw_error = 1'b1 ;
457463
end
464+
465+
default: ;
458466
endcase
459467
end
460468
end
@@ -484,13 +492,16 @@ module axi_dw_downsizer #(
484492

485493
case (r_req_d.ar.burst)
486494
axi_pkg::BURST_INCR : begin
495+
automatic addr_t size_mask;
496+
automatic addr_t conv_ratio;
497+
automatic addr_t align_adj;
487498
// Evaluate downsize ratio
488-
automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ;
489-
automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
499+
size_mask = (1 << r_req_d.ar.size) - 1 ;
500+
conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
490501

491502
// Evaluate output burst length
492-
automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
493-
r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ;
503+
align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
504+
r_req_d.burst_len = (r_req_d.ar.len + 1) * conv_ratio - align_adj - 1 ;
494505

495506
if (conv_ratio != 1) begin
496507
r_req_d.ar.size = AxiMstPortMaxSize;
@@ -508,13 +519,16 @@ module axi_dw_downsizer #(
508519
axi_pkg::BURST_FIXED: begin
509520
// Single transaction
510521
if (r_req_d.ar.len == '0) begin
522+
automatic addr_t size_mask;
523+
automatic addr_t conv_ratio;
524+
automatic addr_t align_adj;
511525
// Evaluate downsize ratio
512-
automatic addr_t size_mask = (1 << r_req_d.ar.size) - 1 ;
513-
automatic addr_t conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
526+
size_mask = (1 << r_req_d.ar.size) - 1 ;
527+
conv_ratio = ((1 << r_req_d.ar.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
514528

515529
// Evaluate output burst length
516-
automatic addr_t align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
517-
r_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0;
530+
align_adj = (r_req_d.ar.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
531+
r_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0;
518532

519533
if (conv_ratio != 1) begin
520534
r_state_d = R_INCR_DOWNSIZE ;
@@ -533,6 +547,8 @@ module axi_dw_downsizer #(
533547
r_state_d = R_PASSTHROUGH;
534548
r_req_d.ar_throw_error = 1'b1 ;
535549
end
550+
551+
default: ;
536552
endcase
537553
end
538554

@@ -553,8 +569,10 @@ module axi_dw_downsizer #(
553569
mst_r_ready_tran[t] = 1'b1;
554570

555571
if (mst_resp.r_valid) begin
556-
automatic addr_t mst_port_offset = AxiMstPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(AxiMstPortStrbWidth)-1:0];
557-
automatic addr_t slv_port_offset = AxiSlvPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(AxiSlvPortStrbWidth)-1:0];
572+
automatic addr_t mst_port_offset;
573+
automatic addr_t slv_port_offset;
574+
mst_port_offset = AxiMstPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(AxiMstPortStrbWidth)-1:0];
575+
slv_port_offset = AxiSlvPortStrbWidth == 1 ? '0 : r_req_q.ar.addr[idx_width(AxiSlvPortStrbWidth)-1:0];
558576

559577
// Serialization
560578
for (int b = 0; b < AxiSlvPortStrbWidth; b++) begin
@@ -577,7 +595,7 @@ module axi_dw_downsizer #(
577595

578596
case (r_req_d.ar.burst)
579597
axi_pkg::BURST_INCR: begin
580-
r_req_d.ar.addr = aligned_addr(r_req_q.ar.addr, r_req_q.ar.size) + (1 << r_req_q.ar.size);
598+
r_req_d.ar.addr = aligned_addr(axi_pkg::largest_addr_t'(r_req_q.ar.addr), r_req_q.ar.size) + (1 << r_req_q.ar.size);
581599
end
582600
axi_pkg::BURST_FIXED: begin
583601
r_req_d.ar.addr = r_req_q.ar.addr;
@@ -597,8 +615,8 @@ module axi_dw_downsizer #(
597615
R_INCR_DOWNSIZE, R_SPLIT_INCR_DOWNSIZE: begin
598616
// Forward when the burst is finished, or after filling up a word
599617
if (r_req_q.burst_len == 0 ||
600-
(aligned_addr(r_req_d.ar.addr, r_req_q.orig_ar_size) !=
601-
aligned_addr(r_req_q.ar.addr, r_req_q.orig_ar_size) )) begin
618+
(aligned_addr(axi_pkg::largest_addr_t'(r_req_d.ar.addr), r_req_q.orig_ar_size) !=
619+
aligned_addr(axi_pkg::largest_addr_t'(r_req_q.ar.addr), r_req_q.orig_ar_size) )) begin
602620
r_req_d.r_valid = 1'b1;
603621
end
604622
end
@@ -623,6 +641,8 @@ module axi_dw_downsizer #(
623641
end
624642
end
625643
end
644+
645+
default: ;
626646
endcase
627647
end
628648

@@ -742,8 +762,10 @@ module axi_dw_downsizer #(
742762
// Request was accepted
743763
if (!w_req_q.aw_valid) begin
744764
if (slv_req_i.w_valid) begin
745-
automatic logic [idx_width(AxiMstPortStrbWidth)-1:0] mst_port_offset = AxiMstPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(AxiMstPortStrbWidth)-1:0];
746-
automatic logic [idx_width(AxiSlvPortStrbWidth)-1:0] slv_port_offset = AxiSlvPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(AxiSlvPortStrbWidth)-1:0];
765+
automatic logic [idx_width(AxiMstPortStrbWidth)-1:0] mst_port_offset;
766+
automatic logic [idx_width(AxiSlvPortStrbWidth)-1:0] slv_port_offset;
767+
mst_port_offset = AxiMstPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(AxiMstPortStrbWidth)-1:0];
768+
slv_port_offset = AxiSlvPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(AxiSlvPortStrbWidth)-1:0];
747769

748770
// Valid output
749771
mst_req.w_valid = !(forward_b_beat_full && w_req_q.aw.len == 0);
@@ -770,7 +792,7 @@ module axi_dw_downsizer #(
770792

771793
case (w_req_d.aw.burst)
772794
axi_pkg::BURST_INCR: begin
773-
w_req_d.aw.addr = aligned_addr(w_req_q.aw.addr, w_req_q.aw.size) + (1 << w_req_q.aw.size);
795+
w_req_d.aw.addr = aligned_addr(axi_pkg::largest_addr_t'(w_req_q.aw.addr), w_req_q.aw.size) + (1 << w_req_q.aw.size);
774796
end
775797
axi_pkg::BURST_FIXED: begin
776798
w_req_d.aw.addr = w_req_q.aw.addr;
@@ -784,8 +806,8 @@ module axi_dw_downsizer #(
784806

785807
W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE: begin
786808
if (w_req_q.burst_len == 0 ||
787-
(aligned_addr(w_req_d.aw.addr, w_req_q.orig_aw_size) !=
788-
aligned_addr(w_req_q.aw.addr, w_req_q.orig_aw_size) )) begin
809+
(aligned_addr(axi_pkg::largest_addr_t'(w_req_d.aw.addr), w_req_q.orig_aw_size) !=
810+
aligned_addr(axi_pkg::largest_addr_t'(w_req_q.aw.addr), w_req_q.orig_aw_size) )) begin
789811
slv_resp_o.w_ready = 1'b1;
790812
end
791813
end
@@ -812,6 +834,7 @@ module axi_dw_downsizer #(
812834
end
813835
end
814836
end
837+
default: ;
815838
endcase
816839

817840
// Can start a new request as soon as w_state_d is W_IDLE
@@ -845,13 +868,16 @@ module axi_dw_downsizer #(
845868

846869
case (slv_req_i.aw.burst)
847870
axi_pkg::BURST_INCR: begin
871+
automatic addr_t size_mask;
872+
automatic addr_t conv_ratio;
873+
automatic addr_t align_adj;
848874
// Evaluate downsize ratio
849-
automatic addr_t size_mask = (1 << slv_req_i.aw.size) - 1 ;
850-
automatic addr_t conv_ratio = ((1 << slv_req_i.aw.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
875+
size_mask = (1 << slv_req_i.aw.size) - 1 ;
876+
conv_ratio = ((1 << slv_req_i.aw.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
851877

852878
// Evaluate output burst length
853-
automatic addr_t align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
854-
w_req_d.burst_len = (slv_req_i.aw.len + 1) * conv_ratio - align_adj - 1 ;
879+
align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
880+
w_req_d.burst_len = (slv_req_i.aw.len + 1) * conv_ratio - align_adj - 1 ;
855881

856882
if (conv_ratio != 1) begin
857883
w_req_d.aw.size = AxiMstPortMaxSize;
@@ -869,13 +895,16 @@ module axi_dw_downsizer #(
869895
axi_pkg::BURST_FIXED: begin
870896
// Single transaction
871897
if (slv_req_i.aw.len == '0) begin
898+
automatic addr_t size_mask;
899+
automatic addr_t conv_ratio;
900+
automatic addr_t align_adj;
872901
// Evaluate downsize ratio
873-
automatic addr_t size_mask = (1 << slv_req_i.aw.size) - 1 ;
874-
automatic addr_t conv_ratio = ((1 << slv_req_i.aw.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
902+
size_mask = (1 << slv_req_i.aw.size) - 1 ;
903+
conv_ratio = ((1 << slv_req_i.aw.size) + AxiMstPortStrbWidth - 1) / AxiMstPortStrbWidth;
875904

876905
// Evaluate output burst length
877-
automatic addr_t align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
878-
w_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0;
906+
align_adj = (slv_req_i.aw.addr & size_mask & ~MstPortByteMask) / AxiMstPortStrbWidth;
907+
w_req_d.burst_len = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0 ;
879908

880909
if (conv_ratio != 1) begin
881910
w_state_d = W_INCR_DOWNSIZE ;
@@ -894,6 +923,8 @@ module axi_dw_downsizer #(
894923
w_state_d = W_PASSTHROUGH;
895924
w_req_d.aw_throw_error = 1'b1 ;
896925
end
926+
927+
default: ;
897928
endcase
898929
end
899930
end

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