feat(esp_hw_support): do esp32p4 l1&l2 cache regs retention by regdma

Author: esp-wzh

components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c

@@ -20,7 +20,6 @@
 #include "freertos/task.h"
 #include "esp_heap_caps.h"
 #include "riscv/csr.h"
-#include "soc/cache_reg.h"
 #include "soc/clic_reg.h"
 #include "soc/rtc_periph.h"
 #include "soc/soc_caps.h"
@@ -32,7 +31,6 @@
 
 #include "esp32p4/rom/ets_sys.h"
 #include "esp32p4/rom/rtc.h"
-#include "esp32p4/rom/cache.h"
 #include "rvsleep-frames.h"
 
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
@@ -76,7 +74,6 @@ typedef struct {
     struct {
         RvCoreCriticalSleepFrame *critical_frame[portNUM_PROCESSORS];
         RvCoreNonCriticalSleepFrame *non_critical_frame[portNUM_PROCESSORS];
-        cpu_domain_dev_sleep_frame_t *cache_config_frame;
         cpu_domain_dev_sleep_frame_t *clic_frame[portNUM_PROCESSORS];
     } retent;
 } sleep_cpu_retention_t;
@@ -107,15 +104,6 @@ static void * cpu_domain_dev_sleep_frame_alloc_and_init(const cpu_domain_dev_reg
     return frame;
 }
 
-static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void)
-{
-    const static cpu_domain_dev_regs_region_t regions[] = {
-        { .start = CACHE_L1_ICACHE_CTRL_REG, .end = CACHE_L1_BYPASS_CACHE_CONF_REG + 4 },
-        { .start = CACHE_L2_CACHE_CTRL_REG, .end = CACHE_L2_CACHE_BLOCKSIZE_CONF_REG + 4 }
-    };
-    return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
-}
-
 static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
 {
     const static cpu_domain_dev_regs_region_t regions[portNUM_PROCESSORS][2] = {
@@ -146,13 +134,6 @@ static esp_err_t esp_sleep_cpu_retention_init_impl(void)
             s_cpu_retention.retent.non_critical_frame[core_id] = (RvCoreNonCriticalSleepFrame *)frame;
         }
     }
-    if (s_cpu_retention.retent.cache_config_frame == NULL) {
-        void *frame = cpu_domain_cache_config_sleep_frame_alloc_and_init();
-        if (frame == NULL) {
-            goto err;
-        }
-        s_cpu_retention.retent.cache_config_frame = (cpu_domain_dev_sleep_frame_t *)frame;
-    }
     for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
         if (s_cpu_retention.retent.clic_frame[core_id] == NULL) {
             void *frame = cpu_domain_clic_sleep_frame_alloc_and_init(core_id);
@@ -186,10 +167,6 @@ static esp_err_t esp_sleep_cpu_retention_deinit_impl(void)
             s_cpu_retention.retent.non_critical_frame[core_id] = NULL;
         }
     }
-    if (s_cpu_retention.retent.cache_config_frame) {
-        heap_caps_free((void *)s_cpu_retention.retent.cache_config_frame);
-        s_cpu_retention.retent.cache_config_frame = NULL;
-    }
     for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
         if (s_cpu_retention.retent.clic_frame[core_id]) {
             heap_caps_free((void *)s_cpu_retention.retent.clic_frame[core_id]);
@@ -442,7 +419,6 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
     atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START);
 #endif
     cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame[core_id]);
-    cpu_domain_dev_regs_save(s_cpu_retention.retent.cache_config_frame);
     rv_core_noncritical_regs_save();
 
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
@@ -468,7 +444,6 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
 #endif
 
     rv_core_noncritical_regs_restore();
-    cpu_domain_dev_regs_restore(s_cpu_retention.retent.cache_config_frame);
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame[core_id]);
     restore_mstatus(mstatus);
 
@@ -495,7 +470,6 @@ bool cpu_domain_pd_allowed(void)
         allowed &= (s_cpu_retention.retent.critical_frame[core_id] != NULL);
         allowed &= (s_cpu_retention.retent.non_critical_frame[core_id] != NULL);
     }
-    allowed &= (s_cpu_retention.retent.cache_config_frame != NULL);
     for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
         allowed &= (s_cpu_retention.retent.clic_frame[core_id] != NULL);
     }

components/esp_hw_support/sleep_system_peripheral.c

@@ -101,11 +101,11 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_systimer_retention_ini
     return ESP_OK;
 }
 
-#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-esp_err_t sleep_sys_periph_l2_cache_retention_init(void)
+#if SOC_PM_CACHE_RETENTION_BY_PAU
+esp_err_t sleep_sys_periph_cache_retention_init(void)
 {
-    esp_err_t err = sleep_retention_entries_create(l2_cache_regs_retention, ARRAY_SIZE(l2_cache_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_HIGH, SLEEP_RETENTION_MODULE_SYS_PERIPH);
-    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (L2 Cache) retention");
+    esp_err_t err = sleep_retention_entries_create(cache_regs_retention, ARRAY_SIZE(cache_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_HIGH, SLEEP_RETENTION_MODULE_SYS_PERIPH);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (Cache) retention");
     ESP_LOGI(TAG, "L2 Cache sleep retention initialization");
     return ESP_OK;
 }
@@ -128,8 +128,8 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
     if(err) goto error;
     err = sleep_sys_periph_hp_system_retention_init(arg);
     if(err) goto error;
-#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-    err = sleep_sys_periph_l2_cache_retention_init();
+#if SOC_PM_CACHE_RETENTION_BY_PAU
+    err = sleep_sys_periph_cache_retention_init();
     if(err) goto error;
 #endif
 #if SOC_APM_SUPPORTED

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1923,6 +1923,10 @@ config SOC_PM_CPU_RETENTION_BY_SW
     bool
     default y
 
+config SOC_PM_CACHE_RETENTION_BY_PAU
+    bool
+    default y
+
 config SOC_PM_PAU_LINK_NUM
     int
     default 4

components/soc/esp32p4/include/soc/soc_caps.h

@@ -718,6 +718,7 @@
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
 #define SOC_PM_CPU_RETENTION_BY_SW      (1)
+#define SOC_PM_CACHE_RETENTION_BY_PAU   (1)
 
 #define SOC_PM_PAU_LINK_NUM             (4)
 #define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR   (1)

components/soc/esp32p4/include/soc/system_periph_retention.h

@@ -26,14 +26,14 @@ extern "C"
 extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
 
 /**
- * @brief Provide access to l2_cache configuration registers retention
+ * @brief Provide access to cache configuration registers retention
  * context definition.
  *
  * This is an internal function of the sleep retention driver, and is not
  * useful for external use.
  */
-#define L2_CACHE_RETENTION_LINK_LEN 1
-extern const regdma_entries_config_t l2_cache_regs_retention[L2_CACHE_RETENTION_LINK_LEN];
+#define CACHE_RETENTION_LINK_LEN 2
+extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN];
 
 /**
  * @brief Provide access to hp_system configuration registers retention
@@ -93,7 +93,7 @@ extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_
  * useful for external use.
  */
 #define PAU_RETENTION_LINK_LEN 1
-extern const regdma_entries_config_t pau_regs_retention[L2_CACHE_RETENTION_LINK_LEN];
+extern const regdma_entries_config_t pau_regs_retention[PAU_RETENTION_LINK_LEN];
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/system_retention_periph.c

@@ -32,17 +32,42 @@ const regdma_entries_config_t intr_matrix_regs_retention[] = {
 };
 _Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
 
+/* L1 Cache Registers Context */
+/*  CACHE_L1_ICACHE_CTRL_REG & CACHE_L1_DCACHE_CTRL_REG & CACHE_L1_BYPASS_CACHE_CONF_REG &
+    CACHE_L1_CACHE_ACS_FAIL_CTRL_REG & CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG*/
+#define L1_CACHE_RETENTION_REGS_CNT     (5)
+#define L1_CACHE_RETENTION_REGS_BASE    (CACHE_L1_ICACHE_CTRL_REG)
+static const uint32_t l1_cache_regs_map[4] = {0x7, 0x0, 0xc000000, 0x0};
 /* L2 Cache Registers Context */
-#define N_REGS_L2_CACHE()      (((CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG - CACHE_L2_CACHE_CTRL_REG) / 4) + 1)
-const regdma_entries_config_t l2_cache_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), CACHE_L2_CACHE_CTRL_REG, CACHE_L2_CACHE_CTRL_REG, N_REGS_L2_CACHE(), 0, 0), .owner = ENTRY(0) }  /* hp system */
+/*  CACHE_L2_CACHE_CTRL_REG & CACHE_L2_BYPASS_CACHE_CONF_REG &
+    CACHE_L2_CACHE_CACHESIZE_CONF_REG & CACHE_L2_CACHE_BLOCKSIZE_CONF_REG &
+    CACHE_L2_CACHE_ACS_FAIL_CTRL_REG & CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG */
+#define L2_CACHE_RETENTION_REGS_CNT     (6)
+#define L2_CACHE_RETENTION_REGS_BASE    (CACHE_L2_CACHE_CTRL_REG)
+static const uint32_t l2_cache_regs_map[4] = {0xc000000f, 0x0, 0x0, 0x0};
+const regdma_entries_config_t cache_regs_retention[] = {
+    [0] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x00), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \
+                                            L1_CACHE_RETENTION_REGS_CNT, 0, 0,              \
+                                            l1_cache_regs_map[0], l1_cache_regs_map[1],     \
+                                            l1_cache_regs_map[2], l1_cache_regs_map[3]),    \
+        .owner = ENTRY(0)
+    },
+    [1] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x01),                                    \
+                                            L2_CACHE_RETENTION_REGS_BASE, L2_CACHE_RETENTION_REGS_BASE, \
+                                            L2_CACHE_RETENTION_REGS_CNT, 0, 0,                          \
+                                            l2_cache_regs_map[0], l2_cache_regs_map[1],                 \
+                                            l2_cache_regs_map[2], l2_cache_regs_map[3]),                \
+        .owner = ENTRY(0)
+    },
 };
-_Static_assert(ARRAY_SIZE(l2_cache_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");
+_Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");
 
 /* HP System Registers Context */
 #define N_REGS_HP_SYSTEM()      (((HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG - DR_REG_HP_SYS_BASE) / 4) + 1)
 const regdma_entries_config_t hp_system_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYS_BASE, DR_REG_HP_SYS_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) }  /* hp system */
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(2), DR_REG_HP_SYS_BASE, DR_REG_HP_SYS_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) }  /* hp system */
 };
 _Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
 

components/soc/include/soc/regdma.h

@@ -35,6 +35,7 @@ extern "C" {
 #define REGDMA_MODEMLPCON_LINK(_pri)        ((0x03 << 8) | _pri)
 #define REGDMA_PAU_LINK(_pri)               ((0x04 << 8) | _pri)
 
+#define REGDMA_CACHE_LINK(_pri)             ((0x0c << 8) | _pri)
 #define REGDMA_INTMTX_LINK(_pri)            ((0x0d << 8) | _pri)
 #define REGDMA_HPSYS_LINK(_pri)             ((0x0e << 8) | _pri)
 #define REGDMA_TEEAPM_LINK(_pri)            ((0x0f << 8) | _pri)