fix(interrupt): fixed interrupt thresholds not working on C5

Author: ESP-Marius

components/riscv/include/esp_private/interrupt_clic.h

@@ -46,6 +46,27 @@ extern "C" {
 #define MTVT_CSR    0x307
 
 
+#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
+
+/**
+ * The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
+ *  - The interrupt threshold is configured via a memory-mapped register instead of a CSR
+ *  - The mintstatus CSR is at 0x346 instead of 0xFB1 as per the official specification
+ */
+#define INTTHRESH_STANDARD  0
+#define MINTSTATUS_CSR      0x346
+
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+
+/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */
+#define INTTHRESH_STANDARD  1
+#define MINTSTATUS_CSR      0xFB1
+#define MINTTHRESH_CSR      0x347
+
+#else
+    #error "Check the implementation of the CLIC on this target."
+#endif
+
 /**
  * @brief Convert a priority level from 8-bit to NLBITS and NLBITS to 8-bit
  *
@@ -59,11 +80,20 @@ extern "C" {
 #define NLBITS_TO_BYTE(level)   (((level) << NLBITS_SHIFT) | ((1 << NLBITS_SHIFT) - 1))
 
 
+#if INTTHRESH_STANDARD
+/* Helper macro to translate absolute interrupt level to CLIC interrupt threshold bits in the mintthresh reg */
+#define CLIC_INT_THRESH(intlevel)       (NLBITS_TO_BYTE(intlevel))
+
+/* Helper macro to translate a CLIC interrupt threshold bits to an absolute interrupt level */
+#define CLIC_THRESH_TO_INT(intlevel)    (BYTE_TO_NLBITS((intlevel)))
+#else
+/* For the non-standard intthresh implementation the threshold is stored in the upper 8 bits of CLIC_CPU_INT_THRESH reg */
 /* Helper macro to translate absolute interrupt level to CLIC interrupt threshold bits in the mintthresh reg */
 #define CLIC_INT_THRESH(intlevel)       (NLBITS_TO_BYTE(intlevel) << CLIC_CPU_INT_THRESH_S)
 
 /* Helper macro to translate a CLIC interrupt threshold bits to an absolute interrupt level */
 #define CLIC_THRESH_TO_INT(intlevel)    (BYTE_TO_NLBITS((intlevel >> CLIC_CPU_INT_THRESH_S) & CLIC_CPU_INT_THRESH_V))
+#endif //INTTHRESH_STANDARD
 
 /* Helper macro to set interrupt level RVHAL_EXCM_LEVEL. Used during critical sections */
 #define RVHAL_EXCM_LEVEL_CLIC           (CLIC_INT_THRESH(RVHAL_EXCM_LEVEL - 1))
@@ -72,26 +102,7 @@ extern "C" {
 #define RVHAL_INTR_ENABLE_THRESH_CLIC   (CLIC_INT_THRESH(RVHAL_INTR_ENABLE_THRESH))
 
 
-#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-
-/**
- * The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
- *  - The interrupt threshold is configured via a memory-mapped register instead of a CSR
- *  - The mintstatus CSR is at 0x346 instead of 0xFB1 as per the official specification
- */
-#define INTTHRESH_STANDARD  0
-#define MINTSTATUS_CSR      0x346
-
-#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
-
-/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */
-#define INTTHRESH_STANDARD  1
-#define MINTSTATUS_CSR      0xFB1
-#define MINTTHRESH_CSR      0x347
 
-#else
-    #error "Check the implementation of the CLIC on this target."
-#endif
 
 
 FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)