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L-KAYAL-KAYA
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feat(parlio_rx): support parlio rx on p4
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19 files changed

+238
-91
lines changed

19 files changed

+238
-91
lines changed

‎components/esp_driver_parlio/src/parlio_common.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ parlio_group_t *parlio_acquire_group_handle(int group_id)
4848
}
4949
// hal layer initialize
5050
parlio_hal_init(&group->hal);
51+
group->dma_align = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
52+
group->dma_align = group->dma_align < 4 ? 4 : group->dma_align;
5153
}
5254
} else { // group already install
5355
group = s_platform.groups[group_id];

‎components/esp_driver_parlio/src/parlio_private.h‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@
3030
#else
3131
#define PARLIO_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
3232
#endif
33+
#define PARLIO_DMA_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
3334

3435
#if SOC_PARLIO_TX_RX_SHARE_INTERRUPT
3536
#define PARLIO_INTR_ALLOC_FLAG_SHARED ESP_INTR_FLAG_SHARED
@@ -57,6 +58,12 @@ typedef dma_descriptor_align8_t parlio_dma_desc_t;
5758

5859
#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
5960

61+
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
62+
#define PARLIO_MAX_ALIGNED_DMA_BUF_SIZE DMA_DESCRIPTOR_BUFFER_MAX_SIZE_64B_ALIGNED
63+
#else
64+
#define PARLIO_MAX_ALIGNED_DMA_BUF_SIZE DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED
65+
#endif
66+
6067
#ifdef CACHE_LL_L2MEM_NON_CACHE_ADDR
6168
/* The descriptor address can be mapped by a fixed offset */
6269
#define PARLIO_GET_NON_CACHED_DESC_ADDR(desc) (desc ? (parlio_dma_desc_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(desc)) : NULL)
@@ -107,11 +114,12 @@ typedef enum {
107114
typedef struct parlio_unit_t *parlio_unit_base_handle_t;
108115

109116
typedef struct parlio_group_t {
110-
int group_id; // group ID, index from 0
111-
portMUX_TYPE spinlock; // to protect per-group register level concurrent access
112-
parlio_hal_context_t hal; // hal layer context
113-
parlio_unit_base_handle_t tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP]; // tx unit handles
114-
parlio_unit_base_handle_t rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP]; // rx unit handles
117+
int group_id; // group ID, index from 0
118+
portMUX_TYPE spinlock; // to protect per-group register level concurrent access
119+
parlio_hal_context_t hal; // hal layer context
120+
uint32_t dma_align; // DMA buffer alignment
121+
parlio_unit_base_handle_t tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP]; // tx unit handles
122+
parlio_unit_base_handle_t rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP]; // rx unit handles
115123
} parlio_group_t;
116124

117125
/**

‎components/esp_driver_parlio/src/parlio_rx.c‎

Lines changed: 129 additions & 43 deletions
Large diffs are not rendered by default.

‎components/esp_driver_parlio/src/parlio_tx.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,7 @@ static void IRAM_ATTR parlio_tx_mount_dma_data(parlio_tx_unit_t *tx_unit, const
405405

406406
#if CONFIG_IDF_TARGET_ESP32P4
407407
// Write back to cache to synchronize the cache before DMA start
408-
esp_cache_msync(buffer, len, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
408+
esp_cache_msync((void *)buffer, len, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
409409
#endif // CONFIG_IDF_TARGET_ESP32P4
410410
}
411411

‎components/esp_driver_parlio/test_apps/.build-test-rules.yml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ components/esp_driver_parlio/test_apps/parlio:
44
disable:
55
- if: SOC_PARLIO_SUPPORTED != 1
66
disable_test:
7-
- if: IDF_TARGET == "esp32p4"
7+
- if: IDF_TARGET in ["esp32h2", "esp32p4"]
88
temporary: true
9-
reason: lack of runner
9+
reason: IDF-9806 waiting for the fix of the bit shift issue after reset
1010
depends_components:
1111
- esp_driver_parlio

‎components/esp_driver_parlio/test_apps/parlio/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32-C6 | ESP32-H2 |
2-
| ----------------- | -------- | -------- |
1+
| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 |
2+
| ----------------- | -------- | -------- | -------- |

‎components/esp_driver_parlio/test_apps/parlio/main/test_board.h‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -18,6 +18,7 @@ extern "C" {
1818
#define TEST_PARLIO_CALLBACK_ATTR
1919
#define TEST_PARLIO_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
2020
#endif
21+
#define TEST_PARLIO_DMA_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
2122

2223
#if CONFIG_IDF_TARGET_ESP32C6
2324
#define TEST_CLK_GPIO 10
@@ -42,15 +43,16 @@ extern "C" {
4243
#define TEST_DATA6_GPIO 8
4344
#define TEST_DATA7_GPIO 9
4445
#elif CONFIG_IDF_TARGET_ESP32P4
45-
#define TEST_CLK_GPIO 20
46-
#define TEST_DATA0_GPIO 21
47-
#define TEST_DATA1_GPIO 22
48-
#define TEST_DATA2_GPIO 34
49-
#define TEST_DATA3_GPIO 35
50-
#define TEST_DATA4_GPIO 48
51-
#define TEST_DATA5_GPIO 49
52-
#define TEST_DATA6_GPIO 10
53-
#define TEST_DATA7_GPIO 11
46+
#define TEST_CLK_GPIO 32
47+
#define TEST_VALID_GPIO 36
48+
#define TEST_DATA0_GPIO 20
49+
#define TEST_DATA1_GPIO 21
50+
#define TEST_DATA2_GPIO 22
51+
#define TEST_DATA3_GPIO 23
52+
#define TEST_DATA4_GPIO 45
53+
#define TEST_DATA5_GPIO 46
54+
#define TEST_DATA6_GPIO 47
55+
#define TEST_DATA7_GPIO 48
5456
#else
5557
#error "Unsupported target"
5658
#endif

‎components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c‎

Lines changed: 34 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -17,16 +17,26 @@
1717
#include "driver/spi_master.h"
1818
#include "driver/gpio.h"
1919
#include "hal/gpio_hal.h"
20+
#include "hal/cache_hal.h"
21+
#include "hal/cache_ll.h"
2022
#include "soc/soc_caps.h"
2123
#include "soc/i2s_periph.h"
2224
#include "soc/spi_periph.h"
2325
#include "soc/parlio_periph.h"
26+
#include "esp_dma_utils.h"
2427
#include "esp_attr.h"
2528
#include "test_board.h"
2629

2730
#define TEST_SPI_HOST SPI2_HOST
2831
#define TEST_I2S_PORT I2S_NUM_0
2932
#define TEST_VALID_SIG (PARLIO_RX_UNIT_MAX_DATA_WIDTH - 1)
33+
34+
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
35+
#define TEST_OUTPUT_CLK_PIN TEST_CLK_GPIO
36+
#else
37+
#define TEST_OUTPUT_CLK_PIN -1
38+
#endif
39+
3040
#define TEST_DEFAULT_UNIT_CONFIG(_clk_src, _clk_freq) { \
3141
.trans_queue_depth = 10, \
3242
.max_recv_size = 10 * 1024, \
@@ -35,7 +45,7 @@
3545
.ext_clk_freq_hz = _clk_src == PARLIO_CLK_SRC_EXTERNAL ? _clk_freq : 0, \
3646
.clk_in_gpio_num = _clk_src == PARLIO_CLK_SRC_EXTERNAL ? TEST_CLK_GPIO : -1, \
3747
.exp_clk_freq_hz = _clk_freq, \
38-
.clk_out_gpio_num = -1, \
48+
.clk_out_gpio_num = _clk_src == PARLIO_CLK_SRC_EXTERNAL ? -1 : TEST_OUTPUT_CLK_PIN, \
3949
.valid_gpio_num = TEST_VALID_GPIO, \
4050
.data_gpio_nums = { \
4151
[0] = TEST_DATA0_GPIO, \
@@ -56,6 +66,10 @@ typedef struct {
5666
uint32_t timeout_cnt;
5767
} test_data_t;
5868

69+
#ifndef ALIGN_UP
70+
#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
71+
#endif
72+
5973
TEST_PARLIO_CALLBACK_ATTR
6074
static bool test_parlio_rx_partial_recv_callback(parlio_rx_unit_handle_t rx_unit, const parlio_rx_event_data_t *edata, void *user_data)
6175
{
@@ -285,11 +299,15 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_
285299
.delimiter = deli,
286300
.flags.partial_rx_en = false,
287301
};
288-
uint8_t recv_buff[TEST_EOF_DATA_LEN];
302+
uint8_t *recv_buff = NULL;
303+
uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
304+
alignment = alignment < 4 ? 4 : alignment;
305+
size_t buff_size = ALIGN_UP(TEST_EOF_DATA_LEN, alignment);
306+
recv_buff = heap_caps_aligned_calloc(alignment, 1, buff_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS);
289307
bool is_success = false;
290308
// sample 5 times
291309
for (int i = 0; i < 5 && !is_success; i++) {
292-
TEST_ESP_OK(parlio_rx_unit_receive(rx_unit, recv_buff, TEST_EOF_DATA_LEN, &recv_config));
310+
TEST_ESP_OK(parlio_rx_unit_receive(rx_unit, recv_buff, buff_size, &recv_config));
293311
TEST_ESP_OK(parlio_rx_unit_wait_all_done(rx_unit, 5000));
294312
for (int k = 0; k < TEST_EOF_DATA_LEN; k++) {
295313
printf("%x ", recv_buff[k]);
@@ -315,6 +333,7 @@ static bool test_delimiter(parlio_rx_delimiter_handle_t deli, bool free_running_
315333
}
316334
// Delete the sender task
317335
vTaskDelete(sender_task);
336+
free(recv_buff);
318337

319338
TEST_ESP_OK(parlio_rx_unit_disable(rx_unit));
320339
TEST_ESP_OK(parlio_del_rx_unit(rx_unit));
@@ -409,8 +428,7 @@ TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
409428
TEST_ESP_OK(parlio_rx_unit_disable(units[0]));
410429
TEST_ESP_OK(parlio_del_rx_unit(units[0]));
411430
}
412-
413-
#define TEST_PAYLOAD_SIZE 5000
431+
#define TEST_PAYLOAD_SIZE 5120
414432

415433
// This test case uses soft delimiter
416434
TEST_CASE("parallel_rx_unit_receive_transaction_test", "[parlio_rx]")
@@ -444,7 +462,11 @@ TEST_CASE("parallel_rx_unit_receive_transaction_test", "[parlio_rx]")
444462
.delimiter = deli,
445463
.flags.partial_rx_en = false,
446464
};
447-
uint8_t *payload = heap_caps_calloc(1, TEST_PAYLOAD_SIZE, TEST_PARLIO_MEM_ALLOC_CAPS);
465+
uint8_t *payload = NULL;
466+
uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
467+
alignment = alignment < 4 ? 4 : alignment;
468+
size_t payload_size = ALIGN_UP(TEST_PAYLOAD_SIZE, alignment);
469+
payload = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS);
448470
TEST_ASSERT(payload);
449471

450472
printf("Testing one normal transaction...\n");
@@ -535,7 +557,11 @@ TEST_CASE("parallel_rx_unit_receive_timeout_test", "[parlio_rx]")
535557
.delimiter = timeout_deli,
536558
.flags.partial_rx_en = false,
537559
};
538-
uint8_t *payload = heap_caps_calloc(1, TEST_PAYLOAD_SIZE, TEST_PARLIO_MEM_ALLOC_CAPS);
560+
uint8_t *payload = NULL;
561+
uint32_t alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
562+
alignment = alignment < 4 ? 4 : alignment;
563+
size_t payload_size = ALIGN_UP(TEST_PAYLOAD_SIZE, alignment);
564+
payload = heap_caps_aligned_calloc(alignment, 1, payload_size, TEST_PARLIO_DMA_MEM_ALLOC_CAPS);
539565
TEST_ASSERT(payload);
540566

541567
printf("Testing the timeout callback...\n");

‎components/esp_driver_parlio/test_apps/parlio/pytest_parlio_unity.py‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,10 @@
11
# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
22
# SPDX-License-Identifier: CC0-1.0
3-
43
import pytest
54
from pytest_embedded import Dut
65

76

87
@pytest.mark.esp32c6
9-
@pytest.mark.esp32h2
108
@pytest.mark.generic
119
@pytest.mark.parametrize(
1210
'config',

‎components/hal/esp32p4/include/hal/parlio_ll.h‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -213,13 +213,13 @@ static inline void parlio_ll_rx_set_recv_bit_len(parl_io_dev_t *dev, uint32_t bi
213213
* @brief Set the sub mode of the level controlled receive mode
214214
*
215215
* @param dev Parallel IO register base address
216-
* @param active_level Level of the external enable signal, true for active high, false for active low
216+
* @param active_low_en Level of the external enable signal, true for active low, false for active high
217217
*/
218218
__attribute__((always_inline))
219-
static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_level)
219+
static inline void parlio_ll_rx_set_level_recv_mode(parl_io_dev_t *dev, bool active_low_en)
220220
{
221221
dev->rx_mode_cfg.rx_smp_mode_sel = 0;
222-
dev->rx_mode_cfg.rx_ext_en_inv = !active_level; // 0: active low, 1: active high
222+
dev->rx_mode_cfg.rx_ext_en_inv = active_low_en;
223223
}
224224

225225
/**
@@ -359,7 +359,7 @@ static inline void parlio_ll_rx_treat_data_line_as_en(parl_io_dev_t *dev, uint32
359359
}
360360

361361
/**
362-
* @brief Wether to enable the RX clock gating
362+
* @brief whether to enable the RX clock gating
363363
*
364364
* @param dev Parallel IO register base address
365365
* @param en True to enable, False to disable
@@ -519,7 +519,7 @@ static inline void parlio_ll_tx_set_eof_condition(parl_io_dev_t *dev, parlio_ll_
519519
}
520520

521521
/**
522-
* @brief Wether to enable the TX clock gating
522+
* @brief whether to enable the TX clock gating
523523
*
524524
* @note The MSB of TXD will be taken as the gating enable signal
525525
*
@@ -589,7 +589,6 @@ static inline void parlio_ll_tx_set_bus_width(parl_io_dev_t *dev, uint32_t width
589589
{
590590
uint32_t width_sel = 0;
591591
switch (width) {
592-
// TODO: check this field (IDF-8284)
593592
case 16:
594593
width_sel = 4;
595594
break;

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