Merge branch 'change/improve_xip_docs_on_p4_v5.3' into 'release/v5.3'

psram: improved xip psram docs on p4 (v5.3)

See merge request espressif/esp-idf!32384

Author: suda-morris

components/esp_psram/esp32p4/Kconfig.spiram

@@ -57,7 +57,7 @@ menu "PSRAM config"
             PSRAM
 
     config SPIRAM_XIP_FROM_PSRAM
-        bool "Enable Executable in place from (XiP) from PSRAM feature"
+        bool "Enable Executable in place from (XiP) from PSRAM feature (READ HELP)"
         default n
         select SPIRAM_FETCH_INSTRUCTIONS
         select SPIRAM_RODATA
@@ -70,7 +70,12 @@ menu "PSRAM config"
             does not have to be placed in IRAM. Therefore codes that need to be executing during Flash
             operations can continue working normally.
 
-            Enabling this option will have better performance (see External RAM documentation for more details).
+            Because P4 flash and PSRAM are using two separate SPI buses, moving flash content to PSRAM will
+            actually increase the load of the PSRAM MSPI bus, so the exact impact on performance will be dependent
+            on your app usage of PSRAM. For example, as the PSRAM bus speed could be much faster than flash bus speed,
+            if the instructions and data that are used to be in flash are not accessed very frequently, you might
+            get better performance with this option enabled. We suggest doing performance profiling to determine
+            if enabling this option.
 
     config SPIRAM_FLASH_LOAD_TO_PSRAM
         bool

docs/en/api-guides/external-ram.rst

@@ -184,8 +184,7 @@ Remaining external RAM can also be added to the capability heap allocator using
 
         The :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` option enables the executable in place (XiP) from PSRAM feature. With this option sections that are normally placed in flash ,``.text`` (for instructions) and ``.rodata`` (for read only data), will be loaded in PSRAM.
 
-        With this option enabled, the cache will not be disabled during an SPI1 flash operation, so code that requires executing during an SPI1 Flash operation does not have to be placed in internal RAM. Because P4 Flash and PSRAM are using two separate SPI buses, moving Flash content to PSRAM will actually increase the load of the PSRAM MSPI bus, so the access speed is relatively slower. The exact impact on performance will be very dependent on your apps usage of PSRAM, and we suggest doing performance profiling to determine if enabling this option will significantly impact your app's performance.
-
+        With this option enabled, the cache will not be disabled during an SPI1 flash operation, so code that requires executing during an SPI1 flash operation does not have to be placed in internal RAM. Because P4 flash and PSRAM are using two separate SPI buses, moving flash content to PSRAM will actually increase the load of the PSRAM MSPI bus, so the exact impact on performance will be dependent on your app usage of PSRAM. For example, as the PSRAM bus speed could be much faster than flash bus speed, if the instructions and data that are used to be in flash are not accessed very frequently, you might get better performance with this option enabled. We suggest doing performance profiling to determine if enabling this option.
 
 Restrictions
 ============