Merge branch 'fix/increase_26mhz_esp32c2_slow_clock_calibration_wdt_threshold_v5.3' into 'release/v5.3'

fix(esp_system): increase 26Mhz esp32c2 slow clock calibration timeout watchdog threshold (v5.3)

See merge request espressif/esp-idf!30575

Author: jack0c

components/esp_system/port/soc/esp32c2/clk.c

@@ -77,11 +77,16 @@ __attribute__((weak)) void esp_clk_init(void)
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
     // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
-    // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
+    // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec on 40MHz XTAL and 2.5 sec on 26MHz XTAL).
     // This prevents excessive delay before resetting in case the supply voltage is drawdown.
-    // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
+    // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec 40MHz XTAL,
+    //  or 11.72 sec on 26MHz XTAL).
     wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#ifdef CONFIG_XTAL_FREQ_26
+    uint32_t stage_timeout_ticks = (uint32_t)(2500ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
+#else
     uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
+#endif
     wdt_hal_write_protect_disable(&rtc_wdt_ctx);
     wdt_hal_feed(&rtc_wdt_ctx);
     //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same