Skip to content

Commit 8445486

Browse files
Harshal5Harshal5
committed
fix(soc): Cleanup inaccessible SHA registers from the header files
1 parent e207b08 commit 8445486

File tree

4 files changed

+2
-640
lines changed

4 files changed

+2
-640
lines changed

‎components/soc/esp32c5/mp/include/soc/sha_reg.h‎

Lines changed: 0 additions & 144 deletions
Original file line numberDiff line numberDiff line change
@@ -172,150 +172,6 @@ extern "C" {
172172
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
173173
#define SHA_M_MEM_SIZE_BYTES 64
174174

175-
/** SHA_3_MODE_REG register
176-
* Initial configuration register 0.
177-
*/
178-
#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800)
179-
/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0;
180-
* Sha3 mode
181-
*/
182-
#define SHA_3_MODE 0x00000007U
183-
#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S)
184-
#define SHA_3_MODE_V 0x00000007U
185-
#define SHA_3_MODE_S 0
186-
187-
/** SHA_3_CLEAN_M_REG register
188-
* Initial configuration register 1.
189-
*/
190-
#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804)
191-
/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0;
192-
* Clean Message.
193-
*/
194-
#define SHA_3_CLEAN_M (BIT(0))
195-
#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S)
196-
#define SHA_3_CLEAN_M_V 0x00000001U
197-
#define SHA_3_CLEAN_M_S 0
198-
199-
/** SHA_3_DMA_BLOCK_NUM_REG register
200-
* DMA configuration register 0.
201-
*/
202-
#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c)
203-
/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
204-
* DMA-SHA3 block number.
205-
*/
206-
#define SHA_3_DMA_BLOCK_NUM 0x0000003FU
207-
#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S)
208-
#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU
209-
#define SHA_3_DMA_BLOCK_NUM_S 0
210-
211-
/** SHA_3_START_REG register
212-
* Typical SHA3 configuration register 0.
213-
*/
214-
#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810)
215-
/** SHA_3_START : WO; bitpos: [0]; default: 0;
216-
* Start typical sha3.
217-
*/
218-
#define SHA_3_START (BIT(0))
219-
#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S)
220-
#define SHA_3_START_V 0x00000001U
221-
#define SHA_3_START_S 0
222-
223-
/** SHA_3_CONTINUE_REG register
224-
* Typical SHA3 configuration register 1.
225-
*/
226-
#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814)
227-
/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0;
228-
* Continue typical sha3.
229-
*/
230-
#define SHA_3_CONTINUE (BIT(0))
231-
#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S)
232-
#define SHA_3_CONTINUE_V 0x00000001U
233-
#define SHA_3_CONTINUE_S 0
234-
235-
/** SHA_3_BUSY_REG register
236-
* Busy register.
237-
*/
238-
#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818)
239-
/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0;
240-
* Sha3 busy state. 1'b0: idle. 1'b1: busy.
241-
*/
242-
#define SHA_3_BUSY_REG (BIT(0))
243-
#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S)
244-
#define SHA_3_BUSY_REG_V 0x00000001U
245-
#define SHA_3_BUSY_REG_S 0
246-
247-
/** SHA_3_DMA_START_REG register
248-
* DMA configuration register 1.
249-
*/
250-
#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c)
251-
/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0;
252-
* Start dma-sha3.
253-
*/
254-
#define SHA_3_DMA_START (BIT(0))
255-
#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S)
256-
#define SHA_3_DMA_START_V 0x00000001U
257-
#define SHA_3_DMA_START_S 0
258-
259-
/** SHA_3_DMA_CONTINUE_REG register
260-
* DMA configuration register 2.
261-
*/
262-
#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820)
263-
/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
264-
* Continue dma-sha3.
265-
*/
266-
#define SHA_3_DMA_CONTINUE (BIT(0))
267-
#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S)
268-
#define SHA_3_DMA_CONTINUE_V 0x00000001U
269-
#define SHA_3_DMA_CONTINUE_S 0
270-
271-
/** SHA_3_CLEAR_INT_REG register
272-
* Interrupt clear register.
273-
*/
274-
#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824)
275-
/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0;
276-
* Clear sha3 interrupt.
277-
*/
278-
#define SHA_3_CLEAR_INT (BIT(0))
279-
#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S)
280-
#define SHA_3_CLEAR_INT_V 0x00000001U
281-
#define SHA_3_CLEAR_INT_S 0
282-
283-
/** SHA_3_INT_ENA_REG register
284-
* Interrupt enable register.
285-
*/
286-
#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828)
287-
/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0;
288-
* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
289-
*/
290-
#define SHA_3_INT_ENA (BIT(0))
291-
#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S)
292-
#define SHA_3_INT_ENA_V 0x00000001U
293-
#define SHA_3_INT_ENA_S 0
294-
295-
/** SHA_3_SHAKE_LENGTH_REG register
296-
* DMA configuration register 3.
297-
*/
298-
#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c)
299-
/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50;
300-
* SHAKE output hash word length
301-
*/
302-
#define SHA_3_SHAKE_LENGTH 0x000007FFU
303-
#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S)
304-
#define SHA_3_SHAKE_LENGTH_V 0x000007FFU
305-
#define SHA_3_SHAKE_LENGTH_S 0
306-
307-
/** SHA_3_M_OUT_MEM register
308-
* Sha3 hash reg which contains intermediate hash or finial hash.
309-
*/
310-
#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900)
311-
#define SHA_3_M_OUT_MEM_SIZE_BYTES 200
312-
313-
/** SHA_3_M_MEM register
314-
* Sha3 message reg which contains message.
315-
*/
316-
#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00)
317-
#define SHA_3_M_MEM_SIZE_BYTES 200
318-
319175
#ifdef __cplusplus
320176
}
321177
#endif

‎components/soc/esp32c5/mp/include/soc/sha_struct.h‎

Lines changed: 1 addition & 176 deletions
Original file line numberDiff line numberDiff line change
@@ -127,118 +127,6 @@ typedef union {
127127
uint32_t val;
128128
} sha_t_length_reg_t;
129129

130-
/** Type of mode register
131-
* Initial configuration register 0.
132-
*/
133-
typedef union {
134-
struct {
135-
/** mode : R/W; bitpos: [2:0]; default: 0;
136-
* Sha3 mode
137-
*/
138-
uint32_t mode:3;
139-
uint32_t reserved_3:29;
140-
};
141-
uint32_t val;
142-
} sha_3_mode_reg_t;
143-
144-
/** Type of clean_m register
145-
* Initial configuration register 1.
146-
*/
147-
typedef union {
148-
struct {
149-
/** clean_m : WO; bitpos: [0]; default: 0;
150-
* Clean Message.
151-
*/
152-
uint32_t clean_m:1;
153-
uint32_t reserved_1:31;
154-
};
155-
uint32_t val;
156-
} sha_3_clean_m_reg_t;
157-
158-
/** Type of dma_block_num register
159-
* DMA configuration register 0.
160-
*/
161-
typedef union {
162-
struct {
163-
/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
164-
* DMA-SHA3 block number.
165-
*/
166-
uint32_t dma_block_num:6;
167-
uint32_t reserved_6:26;
168-
};
169-
uint32_t val;
170-
} sha_3_dma_block_num_reg_t;
171-
172-
/** Type of start register
173-
* Typical SHA3 configuration register 0.
174-
*/
175-
typedef union {
176-
struct {
177-
/** start : WO; bitpos: [0]; default: 0;
178-
* Start typical sha3.
179-
*/
180-
uint32_t start:1;
181-
uint32_t reserved_1:31;
182-
};
183-
uint32_t val;
184-
} sha_3_start_reg_t;
185-
186-
/** Type of continue register
187-
* Typical SHA3 configuration register 1.
188-
*/
189-
typedef union {
190-
struct {
191-
/** conti : WO; bitpos: [0]; default: 0;
192-
* Continue typical sha3.
193-
*/
194-
uint32_t conti:1;
195-
uint32_t reserved_1:31;
196-
};
197-
uint32_t val;
198-
} sha_3_continue_reg_t;
199-
200-
/** Type of dma_start register
201-
* DMA configuration register 1.
202-
*/
203-
typedef union {
204-
struct {
205-
/** dma_start : WO; bitpos: [0]; default: 0;
206-
* Start dma-sha3.
207-
*/
208-
uint32_t dma_start:1;
209-
uint32_t reserved_1:31;
210-
};
211-
uint32_t val;
212-
} sha_3_dma_start_reg_t;
213-
214-
/** Type of dma_continue register
215-
* DMA configuration register 2.
216-
*/
217-
typedef union {
218-
struct {
219-
/** dma_continue : WO; bitpos: [0]; default: 0;
220-
* Continue dma-sha3.
221-
*/
222-
uint32_t dma_continue:1;
223-
uint32_t reserved_1:31;
224-
};
225-
uint32_t val;
226-
} sha_3_dma_continue_reg_t;
227-
228-
/** Type of shake_length register
229-
* DMA configuration register 3.
230-
*/
231-
typedef union {
232-
struct {
233-
/** shake_length : WO; bitpos: [10:0]; default: 50;
234-
* SHAKE output hash word length
235-
*/
236-
uint32_t shake_length:11;
237-
uint32_t reserved_11:21;
238-
};
239-
uint32_t val;
240-
} sha_3_shake_length_reg_t;
241-
242130

243131
/** Group: Status Registers */
244132
/** Type of busy register
@@ -306,52 +194,6 @@ typedef union {
306194

307195
/** Group: memory type */
308196

309-
/** Group: Status Register */
310-
/** Type of busy register
311-
* Busy register.
312-
*/
313-
typedef union {
314-
struct {
315-
/** busy_reg : RO; bitpos: [0]; default: 0;
316-
* Sha3 busy state. 1'b0: idle. 1'b1: busy.
317-
*/
318-
uint32_t busy_reg:1;
319-
uint32_t reserved_1:31;
320-
};
321-
uint32_t val;
322-
} sha_3_busy_reg_t;
323-
324-
325-
/** Group: Interrupt Register */
326-
/** Type of clear_int register
327-
* Interrupt clear register.
328-
*/
329-
typedef union {
330-
struct {
331-
/** clear_int : WO; bitpos: [0]; default: 0;
332-
* Clear sha3 interrupt.
333-
*/
334-
uint32_t clear_int:1;
335-
uint32_t reserved_1:31;
336-
};
337-
uint32_t val;
338-
} sha_3_clear_int_reg_t;
339-
340-
/** Type of int_ena register
341-
* Interrupt enable register.
342-
*/
343-
typedef union {
344-
struct {
345-
/** int_ena : R/W; bitpos: [0]; default: 0;
346-
* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
347-
*/
348-
uint32_t int_ena:1;
349-
uint32_t reserved_1:31;
350-
};
351-
uint32_t val;
352-
} sha_3_int_ena_reg_t;
353-
354-
355197
typedef struct {
356198
volatile sha_mode_reg_t mode;
357199
volatile sha_t_string_reg_t t_string;
@@ -368,29 +210,12 @@ typedef struct {
368210
uint32_t reserved_030[4];
369211
volatile uint32_t h[16];
370212
volatile uint32_t m[16];
371-
uint32_t reserved_0c0[464];
372-
volatile sha_3_mode_reg_t mode_3;
373-
volatile sha_3_clean_m_reg_t clean_m_3;
374-
uint32_t reserved_808;
375-
volatile sha_3_dma_block_num_reg_t dma_block_num_3;
376-
volatile sha_3_start_reg_t start_3;
377-
volatile sha_3_continue_reg_t continue_3;
378-
volatile sha_3_busy_reg_t busy_3;
379-
volatile sha_3_dma_start_reg_t dma_start_3;
380-
volatile sha_3_dma_continue_reg_t dma_continue_3;
381-
volatile sha_3_clear_int_reg_t clear_int_3;
382-
volatile sha_3_int_ena_reg_t int_ena_3;
383-
volatile sha_3_shake_length_reg_t shake_length_3;
384-
uint32_t reserved_830[52];
385-
volatile uint32_t m_out_3[50];
386-
uint32_t reserved_9c8[14];
387-
volatile uint32_t m_3[50];
388213
} sha_dev_t;
389214

390215
extern sha_dev_t SHA;
391216

392217
#ifndef __cplusplus
393-
_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure");
218+
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
394219
#endif
395220

396221
#ifdef __cplusplus

0 commit comments

Comments
 (0)