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Merge branch 'feat/update-memory-layout-c5-mp_v5.3' into 'release/v5.3'
feat(heap): support heap and update memory layout on esp32c5-mp target (backport v5.3) See merge request espressif/esp-idf!31040
2 parents c56b21b + 32c6ee8 commit 6c7c212

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+15
-25
lines changed

4 files changed

+15
-25
lines changed

‎components/heap/port/esp32c5/memory_layout.c‎

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,11 @@ enum {
4545
/**
4646
* Defined the attributes and allocation priority of each memory on the chip,
4747
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
48-
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
48+
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
4949
* in turn to continue matching.
5050
*/
5151
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
52-
/* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */
52+
/* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */
5353
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C5_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
5454
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C5_MEM_COMMON_CAPS, 0 }},
5555
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
@@ -70,23 +70,16 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
7070
/**
7171
* Register the shared buffer area of the last memory block into the heap during heap initialization
7272
*/
73-
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
73+
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
7474

7575
const soc_memory_region_t soc_memory_regions[] = {
7676
#if CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
77-
{ SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW),SOC_MEMORY_TYPE_SPIRAM, 0}, //SPI SRAM, if available
77+
{ SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW), SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
7878
#endif
79-
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory
80-
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory
81-
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
82-
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory
83-
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory
84-
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
85-
{ 0x40840000, (APP_USABLE_DRAM_END-0x40840000), SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level3, can be used as trace memory
86-
#endif
87-
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
79+
{ SOC_DIRAM_DRAM_LOW, (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory
80+
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM, can be used as trace memory (ROM reserved area)
8881
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
89-
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
82+
{ SOC_RTC_DATA_LOW, (SOC_RTC_DATA_HIGH - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
9083
#endif
9184
};
9285

@@ -109,7 +102,6 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
109102
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
110103

111104
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
112-
// TODO: IDF-6019 check reserved lp mem region
113105
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
114106
#endif
115107

@@ -118,5 +110,5 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserv
118110
#ifdef CONFIG_SPIRAM
119111
/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
120112
* memory to heap depending on the actual SPIRAM chip size. */
121-
SOC_RESERVE_MEMORY_REGION(SOC_DROM_LOW, SOC_DROM_HIGH, extram_data_region);
113+
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region);
122114
#endif

‎components/heap/port/esp32c6/memory_layout.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -42,11 +42,11 @@ enum {
4242
/**
4343
* Defined the attributes and allocation priority of each memory on the chip,
4444
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
45-
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
45+
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
4646
* in turn to continue matching.
4747
*/
4848
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
49-
/* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */
49+
/* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */
5050
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
5151
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C6_MEM_COMMON_CAPS, 0 }},
5252
};
@@ -96,7 +96,6 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
9696
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
9797

9898
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
99-
// TODO: IDF-6019 check reserved lp mem region
10099
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
101100
#endif
102101

‎components/heap/port/esp32h2/memory_layout.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -40,11 +40,11 @@ enum {
4040
/**
4141
* Defined the attributes and allocation priority of each memory on the chip,
4242
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
43-
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
43+
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
4444
* in turn to continue matching.
4545
*/
4646
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
47-
/* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */
47+
/* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */
4848
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32H2_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
4949
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32H2_MEM_COMMON_CAPS, 0 }},
5050
};
@@ -95,7 +95,6 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
9595
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
9696

9797
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
98-
// TODO: IDF-6019 check reserved lp mem region
9998
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
10099
#endif
101100

‎components/soc/esp32c5/mp/include/soc/soc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@
208208
#define SOC_DEBUG_HIGH 0x28000000
209209

210210
// Start (highest address) of ROM boot stack, only relevant during early boot
211-
#define SOC_ROM_STACK_START 0x4085c8d0
211+
#define SOC_ROM_STACK_START 0x4085e9a0
212212
#define SOC_ROM_STACK_SIZE 0x2000
213213

214214
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.

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