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feat(hal/usb): Make USB-DWC HAL&LL configuration independent
Previously, we included symbols from soc/usb_dwc_cfg.h and configured the HAL and LL according to it. Now we get the configuration in runtime from USB-DWC registers. Added missing definition for USB FS peripheral on ESP32-P4.
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11 files changed

+344
-257
lines changed

11 files changed

+344
-257
lines changed

‎components/hal/esp32p4/include/hal/usb_dwc_ll.h‎

Lines changed: 30 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
#include <stdint.h>
1010
#include <stdbool.h>
1111
#include "soc/usb_dwc_struct.h"
12-
#include "soc/usb_dwc_cfg.h"
1312
#include "hal/usb_dwc_types.h"
1413
#include "hal/misc.h"
1514

@@ -20,8 +19,7 @@ extern "C" {
2019
/* ----------------------------- Helper Macros ------------------------------ */
2120

2221
// Get USB hardware instance
23-
// TODO: extend this macros when we have support for both FS and HS hardware on P4
24-
#define USB_DWC_LL_GET_HW(num) (&USB_DWC_HS)
22+
#define USB_DWC_LL_GET_HW(num) (((num) == 1) ? &USB_DWC_FS : &USB_DWC_HS)
2523

2624
/* -----------------------------------------------------------------------------
2725
--------------------------------- DWC Constants --------------------------------
@@ -221,11 +219,9 @@ static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t
221219

222220
static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
223221
{
224-
#if (OTG_HSPHY_INTERFACE != 0)
225222
hw->gusbcfg_reg.phyif = 1; // 16 bits interface
226223
hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
227224
hw->gusbcfg_reg.physel = 0; // HS PHY
228-
#endif // (OTG_HSPHY_INTERFACE != 0)
229225
}
230226

231227
// --------------------------- GRSTCTL Register --------------------------------
@@ -352,24 +348,19 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
352348

353349
// --------------------------- GHWCFGx Register --------------------------------
354350

355-
/**
356-
* @brief Get the hardware configuration registers of the DWC_OTG controller
357-
*
358-
* The hardware configuration regitsers are read only and indicate the various
359-
* features of the DWC_OTG core.
360-
*
361-
* @param hw Start address of the DWC_OTG registers
362-
* @param[out] ghwcfg1 Hardware configuration registesr 1
363-
* @param[out] ghwcfg2 Hardware configuration registesr 2
364-
* @param[out] ghwcfg3 Hardware configuration registesr 3
365-
* @param[out] ghwcfg4 Hardware configuration registesr 4
366-
*/
367-
static inline void usb_dwc_ll_ghwcfg_get_hw_config(usb_dwc_dev_t *hw, uint32_t *ghwcfg1, uint32_t *ghwcfg2, uint32_t *ghwcfg3, uint32_t *ghwcfg4)
351+
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
352+
{
353+
return hw->ghwcfg3_reg.dfifodepth;
354+
}
355+
356+
static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
357+
{
358+
return hw->ghwcfg2_reg.hsphytype;
359+
}
360+
361+
static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
368362
{
369-
*ghwcfg1 = hw->ghwcfg1_reg.val;
370-
*ghwcfg2 = hw->ghwcfg2_reg.val;
371-
*ghwcfg3 = hw->ghwcfg3_reg.val;
372-
*ghwcfg4 = hw->ghwcfg4_reg.val;
363+
return hw->ghwcfg2_reg.numhstchnl;
373364
}
374365

375366
// --------------------------- HPTXFSIZ Register -------------------------------
@@ -434,47 +425,44 @@ static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
434425
hw->hcfg_reg.fslssupp = 1;
435426
}
436427

437-
static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
438-
{
439-
hw->hcfg_reg.fslspclksel = 1;
440-
}
441-
442428
/**
443-
* @brief Sets some default values to HCFG to operate in Host mode with scatter/gather DMA
429+
* @brief Set FSLS PHY clock
444430
*
431+
* @attention This function should only be called if FSLS PHY is selected
445432
* @param[in] hw Start address of the DWC_OTG registers
446-
* @param[in] speed Speed to initialize the host port at
447433
*/
448-
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
434+
static inline void usb_dwc_ll_hcfg_set_fsls_phy_clock(usb_dwc_dev_t *hw)
449435
{
450-
hw->hcfg_reg.descdma = 1; //Enable scatt/gatt
451-
#if (OTG_HSPHY_INTERFACE == 0)
452436
/*
453437
Indicate to the OTG core what speed the PHY clock is at
454-
Note: It seems like S2/S3 PHY has an implicit 8 divider applied when in LS mode,
438+
Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
455439
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
456440
*/
457-
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
458-
#endif // (OTG_HSPHY_INTERFACE == 0)
459-
hw->hcfg_reg.perschedena = 0; //Disable perio sched
441+
usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
442+
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;
460443
}
461444

462445
// ----------------------------- HFIR Register ---------------------------------
463446

464-
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
447+
/**
448+
* @brief Set Frame Interval
449+
*
450+
* @attention This function should only be called if FSLS PHY is selected
451+
* @param[in] hw Start address of the DWC_OTG registers
452+
*/
453+
static inline void usb_dwc_ll_hfir_set_frame_interval(usb_dwc_dev_t *hw)
465454
{
466-
#if (OTG_HSPHY_INTERFACE == 0)
467455
usb_dwc_hfir_reg_t hfir;
468456
hfir.val = hw->hfir_reg.val;
469-
hfir.hfirrldctrl = 0; //Disable dynamic loading
457+
hfir.hfirrldctrl = 0; // Disable dynamic loading
470458
/*
471459
Set frame interval to be equal to 1ms
472-
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
460+
Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
473461
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
474462
*/
475-
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
463+
usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
464+
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000;
476465
hw->hfir_reg.val = hfir.val;
477-
#endif // (OTG_HSPHY_INTERFACE == 0)
478466
}
479467

480468
// ----------------------------- HFNUM Register --------------------------------

‎components/hal/esp32s2/include/hal/usb_dwc_ll.h‎

Lines changed: 29 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -220,11 +220,9 @@ static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t
220220

221221
static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
222222
{
223-
#if (OTG_HSPHY_INTERFACE != 0)
224223
hw->gusbcfg_reg.phyif = 1; // 16 bits interface
225224
hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
226225
hw->gusbcfg_reg.physel = 0; // HS PHY
227-
#endif // (OTG_HSPHY_INTERFACE != 0)
228226
}
229227

230228
// --------------------------- GRSTCTL Register --------------------------------
@@ -351,24 +349,19 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
351349

352350
// --------------------------- GHWCFGx Register --------------------------------
353351

354-
/**
355-
* @brief Get the hardware configuration registers of the DWC_OTG controller
356-
*
357-
* The hardware configuration regitsers are read only and indicate the various
358-
* features of the DWC_OTG core.
359-
*
360-
* @param hw Start address of the DWC_OTG registers
361-
* @param[out] ghwcfg1 Hardware configuration registesr 1
362-
* @param[out] ghwcfg2 Hardware configuration registesr 2
363-
* @param[out] ghwcfg3 Hardware configuration registesr 3
364-
* @param[out] ghwcfg4 Hardware configuration registesr 4
365-
*/
366-
static inline void usb_dwc_ll_ghwcfg_get_hw_config(usb_dwc_dev_t *hw, uint32_t *ghwcfg1, uint32_t *ghwcfg2, uint32_t *ghwcfg3, uint32_t *ghwcfg4)
352+
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
353+
{
354+
return hw->ghwcfg3_reg.dfifodepth;
355+
}
356+
357+
static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
358+
{
359+
return hw->ghwcfg2_reg.hsphytype;
360+
}
361+
362+
static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
367363
{
368-
*ghwcfg1 = hw->ghwcfg1_reg.val;
369-
*ghwcfg2 = hw->ghwcfg2_reg.val;
370-
*ghwcfg3 = hw->ghwcfg3_reg.val;
371-
*ghwcfg4 = hw->ghwcfg4_reg.val;
364+
return hw->ghwcfg2_reg.numhstchnl;
372365
}
373366

374367
// --------------------------- HPTXFSIZ Register -------------------------------
@@ -433,47 +426,44 @@ static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
433426
hw->hcfg_reg.fslssupp = 1;
434427
}
435428

436-
static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
437-
{
438-
hw->hcfg_reg.fslspclksel = 1;
439-
}
440-
441429
/**
442-
* @brief Sets some default values to HCFG to operate in Host mode with scatter/gather DMA
430+
* @brief Set FSLS PHY clock
443431
*
432+
* @attention This function should only be called if FSLS PHY is selected
444433
* @param[in] hw Start address of the DWC_OTG registers
445-
* @param[in] speed Speed to initialize the host port at
446434
*/
447-
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
435+
static inline void usb_dwc_ll_hcfg_set_fsls_phy_clock(usb_dwc_dev_t *hw)
448436
{
449-
hw->hcfg_reg.descdma = 1; //Enable scatt/gatt
450-
#if (OTG_HSPHY_INTERFACE == 0)
451437
/*
452438
Indicate to the OTG core what speed the PHY clock is at
453-
Note: It seems like S2/S3 PHY has an implicit 8 divider applied when in LS mode,
439+
Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
454440
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
455441
*/
456-
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
457-
#endif // (OTG_HSPHY_INTERFACE == 0)
458-
hw->hcfg_reg.perschedena = 0; //Disable perio sched
442+
usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
443+
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;
459444
}
460445

461446
// ----------------------------- HFIR Register ---------------------------------
462447

463-
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
448+
/**
449+
* @brief Set Frame Interval
450+
*
451+
* @attention This function should only be called if FSLS PHY is selected
452+
* @param[in] hw Start address of the DWC_OTG registers
453+
*/
454+
static inline void usb_dwc_ll_hfir_set_frame_interval(usb_dwc_dev_t *hw)
464455
{
465-
#if (OTG_HSPHY_INTERFACE == 0)
466456
usb_dwc_hfir_reg_t hfir;
467457
hfir.val = hw->hfir_reg.val;
468-
hfir.hfirrldctrl = 0; //Disable dynamic loading
458+
hfir.hfirrldctrl = 0; // Disable dynamic loading
469459
/*
470460
Set frame interval to be equal to 1ms
471-
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
461+
Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
472462
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
473463
*/
474-
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
464+
usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
465+
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000;
475466
hw->hfir_reg.val = hfir.val;
476-
#endif // (OTG_HSPHY_INTERFACE == 0)
477467
}
478468

479469
// ----------------------------- HFNUM Register --------------------------------

‎components/hal/esp32s3/include/hal/usb_dwc_ll.h‎

Lines changed: 29 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -220,11 +220,9 @@ static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t
220220

221221
static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
222222
{
223-
#if (OTG_HSPHY_INTERFACE != 0)
224223
hw->gusbcfg_reg.phyif = 1; // 16 bits interface
225224
hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
226225
hw->gusbcfg_reg.physel = 0; // HS PHY
227-
#endif // (OTG_HSPHY_INTERFACE != 0)
228226
}
229227

230228
// --------------------------- GRSTCTL Register --------------------------------
@@ -351,24 +349,19 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
351349

352350
// --------------------------- GHWCFGx Register --------------------------------
353351

354-
/**
355-
* @brief Get the hardware configuration registers of the DWC_OTG controller
356-
*
357-
* The hardware configuration regitsers are read only and indicate the various
358-
* features of the DWC_OTG core.
359-
*
360-
* @param hw Start address of the DWC_OTG registers
361-
* @param[out] ghwcfg1 Hardware configuration registesr 1
362-
* @param[out] ghwcfg2 Hardware configuration registesr 2
363-
* @param[out] ghwcfg3 Hardware configuration registesr 3
364-
* @param[out] ghwcfg4 Hardware configuration registesr 4
365-
*/
366-
static inline void usb_dwc_ll_ghwcfg_get_hw_config(usb_dwc_dev_t *hw, uint32_t *ghwcfg1, uint32_t *ghwcfg2, uint32_t *ghwcfg3, uint32_t *ghwcfg4)
352+
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
353+
{
354+
return hw->ghwcfg3_reg.dfifodepth;
355+
}
356+
357+
static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
358+
{
359+
return hw->ghwcfg2_reg.hsphytype;
360+
}
361+
362+
static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
367363
{
368-
*ghwcfg1 = hw->ghwcfg1_reg.val;
369-
*ghwcfg2 = hw->ghwcfg2_reg.val;
370-
*ghwcfg3 = hw->ghwcfg3_reg.val;
371-
*ghwcfg4 = hw->ghwcfg4_reg.val;
364+
return hw->ghwcfg2_reg.numhstchnl;
372365
}
373366

374367
// --------------------------- HPTXFSIZ Register -------------------------------
@@ -433,47 +426,44 @@ static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
433426
hw->hcfg_reg.fslssupp = 1;
434427
}
435428

436-
static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
437-
{
438-
hw->hcfg_reg.fslspclksel = 1;
439-
}
440-
441429
/**
442-
* @brief Sets some default values to HCFG to operate in Host mode with scatter/gather DMA
430+
* @brief Set FSLS PHY clock
443431
*
432+
* @attention This function should only be called if FSLS PHY is selected
444433
* @param[in] hw Start address of the DWC_OTG registers
445-
* @param[in] speed Speed to initialize the host port at
446434
*/
447-
static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
435+
static inline void usb_dwc_ll_hcfg_set_fsls_phy_clock(usb_dwc_dev_t *hw)
448436
{
449-
hw->hcfg_reg.descdma = 1; //Enable scatt/gatt
450-
#if (OTG_HSPHY_INTERFACE == 0)
451437
/*
452438
Indicate to the OTG core what speed the PHY clock is at
453-
Note: It seems like S2/S3 PHY has an implicit 8 divider applied when in LS mode,
439+
Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
454440
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
455441
*/
456-
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
457-
#endif // (OTG_HSPHY_INTERFACE == 0)
458-
hw->hcfg_reg.perschedena = 0; //Disable perio sched
442+
usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
443+
hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;
459444
}
460445

461446
// ----------------------------- HFIR Register ---------------------------------
462447

463-
static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
448+
/**
449+
* @brief Set Frame Interval
450+
*
451+
* @attention This function should only be called if FSLS PHY is selected
452+
* @param[in] hw Start address of the DWC_OTG registers
453+
*/
454+
static inline void usb_dwc_ll_hfir_set_frame_interval(usb_dwc_dev_t *hw)
464455
{
465-
#if (OTG_HSPHY_INTERFACE == 0)
466456
usb_dwc_hfir_reg_t hfir;
467457
hfir.val = hw->hfir_reg.val;
468-
hfir.hfirrldctrl = 0; //Disable dynamic loading
458+
hfir.hfirrldctrl = 0; // Disable dynamic loading
469459
/*
470460
Set frame interval to be equal to 1ms
471-
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
461+
Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
472462
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
473463
*/
474-
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
464+
usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
465+
hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000;
475466
hw->hfir_reg.val = hfir.val;
476-
#endif // (OTG_HSPHY_INTERFACE == 0)
477467
}
478468

479469
// ----------------------------- HFNUM Register --------------------------------

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