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change(esp_hw_support): switch to sleep_flags earlier to identify sleep state
1 parent 87c4227 commit 67a4de4

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13 files changed

+271
-271
lines changed

13 files changed

+271
-271
lines changed

‎components/esp_hw_support/include/esp_private/esp_pmu.h‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -46,11 +46,11 @@ typedef enum {
4646
#define RTC_SLEEP_PD_MODEM PMU_SLEEP_PD_MODEM //!< Power down modem(include wifi, ble and 15.4)
4747

4848
//These flags are not power domains, but will affect some sleep parameters
49-
#define RTC_SLEEP_DIG_USE_8M BIT(16)
50-
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
51-
#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
52-
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(19)
53-
#define RTC_SLEEP_LP_PERIPH_USE_XTAL BIT(20)
49+
#define RTC_SLEEP_DIG_USE_8M BIT(27)
50+
#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(28)
51+
#define RTC_SLEEP_NO_ULTRA_LOW BIT(29) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
52+
#define RTC_SLEEP_XTAL_AS_RTC_FAST BIT(30)
53+
#define RTC_SLEEP_LP_PERIPH_USE_XTAL BIT(31)
5454

5555
#if SOC_PM_SUPPORT_EXT0_WAKEUP
5656
#define RTC_EXT0_TRIG_EN PMU_EXT0_WAKEUP_EN //!< EXT0 wakeup
@@ -205,40 +205,40 @@ bool pmu_sleep_pll_already_enabled(void);
205205
/**
206206
* @brief Calculate the LP system hardware time overhead during sleep
207207
*
208-
* @param pd_flags flags indicates the power domain that will be powered down
208+
* @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
209209
* @param slowclk_period re-calibrated slow clock period
210210
* @param fastclk_period re-calibrated fast clock period
211211
*
212212
* @return hardware time overhead in us
213213
*/
214-
uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
214+
uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
215215

216216
/**
217217
* @brief Calculate the HP system hardware time overhead during sleep
218218
*
219-
* @param pd_flags flags indicates the power domain that will be powered down
219+
* @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
220220
* @param slowclk_period re-calibrated slow clock period
221221
* @param fastclk_period re-calibrated fast clock period
222222
*
223223
* @return hardware time overhead in us
224224
*/
225-
uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
225+
uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
226226

227227
/**
228228
* @brief Calculate the hardware time overhead during sleep to compensate for sleep time
229229
*
230-
* @param pd_flags flags indicates the power domain that will be powered down
230+
* @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
231231
* @param slowclk_period re-calibrated slow clock period
232232
* @param fastclk_period re-calibrated fast clock period
233233
*
234234
* @return hardware time overhead in us
235235
*/
236-
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
236+
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
237237

238238
/**
239239
* @brief Get default sleep configuration
240240
* @param config pmu_sleep_config instance
241-
* @param pd_flags flags indicates the power domain that will be powered down
241+
* @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
242242
* @param adjustment total software and hardware time overhead
243243
* @param slowclk_period re-calibrated slow clock period in microseconds,
244244
* Q13.19 fixed point format
@@ -248,7 +248,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
248248
249249
* @return hardware time overhead in us
250250
*/
251-
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t pd_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
251+
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
252252

253253
/**
254254
* @brief Prepare the chip to enter sleep mode

‎components/esp_hw_support/port/esp32c5/pmu_sleep.c‎

Lines changed: 13 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -51,14 +51,14 @@ void pmu_sleep_disable_regdma_backup(void)
5151
}
5252
}
5353

54-
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
54+
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
5555
{
5656
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
5757

5858
/* LP core hardware wait time, microsecond */
5959
const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
6060
const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
61-
const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
61+
const int lp_clk_power_on_wait_time_us = (sleep_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
6262
: rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
6363
const int lp_control_wait_time_us = mc->lp.isolate_wait_time_us + mc->lp.reset_wait_time_us;
6464

@@ -107,7 +107,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
107107
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
108108
pmu_sleep_param_config_t *param,
109109
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
110-
const uint32_t pd_flags,
110+
const uint32_t sleep_flags,
111111
const uint32_t adjustment,
112112
const uint32_t slowclk_period,
113113
const uint32_t fastclk_period
@@ -123,7 +123,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
123123
param->hp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period);
124124
param->hp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period);
125125

126-
const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
126+
const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
127127
const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
128128
const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
129129
param->hp_sys.modem_wakeup_wait_cycle = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
@@ -145,36 +145,30 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
145145

146146
const pmu_sleep_config_t* pmu_sleep_config_default(
147147
pmu_sleep_config_t *config,
148-
uint32_t pd_flags,
148+
uint32_t sleep_flags,
149149
uint32_t adjustment,
150150
uint32_t slowclk_period,
151151
uint32_t fastclk_period,
152152
bool dslp
153153
)
154154
{
155-
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
156-
157-
uint32_t iram_pd_flags = 0;
158-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0;
159-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0;
160-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0;
161-
iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0;
155+
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
162156
config->power = power_default;
163157

164-
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
165-
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
158+
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
159+
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
166160

167161
if (dslp) {
168162
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
169-
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
163+
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
170164
config->analog = analog_default;
171165
} else {
172-
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags);
166+
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags);
173167
config->digital = digital_default;
174168

175-
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
169+
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
176170

177-
if (!(pd_flags & PMU_SLEEP_PD_XTAL) || !(pd_flags & PMU_SLEEP_PD_RC_FAST)){
171+
if (!(sleep_flags & PMU_SLEEP_PD_XTAL) || !(sleep_flags & PMU_SLEEP_PD_RC_FAST)){
178172
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
179173
analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
180174
analog_default.hp_sys.analog.dbias = HP_CALI_DBIAS_SLP_1V1;

‎components/esp_hw_support/port/esp32c5/private_include/pmu_param.h‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -273,14 +273,14 @@ typedef struct {
273273
} lp_sys[PMU_MODE_LP_MAX];
274274
} pmu_sleep_power_config_t;
275275

276-
#define PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags) { \
276+
#define PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags) { \
277277
.hp_sys = { \
278278
.dig_power = { \
279-
.vdd_spi_pd_en = ((pd_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0, \
280-
.wifi_pd_en = ((pd_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0, \
281-
.cpu_pd_en = ((pd_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0, \
282-
.aon_pd_en = ((pd_flags) & PMU_SLEEP_PD_HP_AON) ? 1 : 0, \
283-
.top_pd_en = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
279+
.vdd_spi_pd_en = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0,\
280+
.wifi_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0,\
281+
.cpu_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0,\
282+
.aon_pd_en = ((sleep_flags) & PMU_SLEEP_PD_HP_AON) ? 1 : 0,\
283+
.top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0,\
284284
.mem_pd_en = 0, \
285285
.mem_dslp = 0 \
286286
}, \
@@ -292,7 +292,7 @@ typedef struct {
292292
.xpd_bbpll = 0 \
293293
}, \
294294
.xtal = { \
295-
.xpd_xtal = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
295+
.xpd_xtal = ((sleep_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
296296
} \
297297
}, \
298298
.lp_sys[PMU_MODE_LP_ACTIVE] = { \
@@ -301,23 +301,23 @@ typedef struct {
301301
.mem_dslp = 0 \
302302
}, \
303303
.clk_power = { \
304-
.xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
305-
.xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
304+
.xpd_xtal32k = ((sleep_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,\
305+
.xpd_rc32k = ((sleep_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
306306
.xpd_fosc = 1 \
307307
} \
308308
}, \
309309
.lp_sys[PMU_MODE_LP_SLEEP] = { \
310310
.dig_power = { \
311-
.peri_pd_en = ((pd_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
311+
.peri_pd_en = ((sleep_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
312312
.mem_dslp = 0 \
313313
}, \
314314
.clk_power = { \
315-
.xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
316-
.xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
317-
.xpd_fosc = ((pd_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1 \
315+
.xpd_xtal32k = ((sleep_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1,\
316+
.xpd_rc32k = ((sleep_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
317+
.xpd_fosc = ((sleep_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1 \
318318
}, \
319319
.xtal = { \
320-
.xpd_xtal = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
320+
.xpd_xtal = ((sleep_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
321321
} \
322322
} \
323323
}
@@ -326,9 +326,9 @@ typedef struct {
326326
pmu_hp_sys_cntl_reg_t syscntl;
327327
} pmu_sleep_digital_config_t;
328328

329-
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags) { \
329+
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \
330330
.syscntl = { \
331-
.dig_pad_slp_sel = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
331+
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
332332
} \
333333
}
334334

@@ -341,7 +341,7 @@ typedef struct {
341341
} lp_sys[PMU_MODE_LP_MAX];
342342
} pmu_sleep_analog_config_t;
343343

344-
#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) { \
344+
#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags) { \
345345
.hp_sys = { \
346346
.analog = { \
347347
.drv_b = PMU_HP_DRVB_LIGHTSLEEP, \
@@ -366,7 +366,7 @@ typedef struct {
366366
} \
367367
}
368368

369-
#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) { \
369+
#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags) { \
370370
.hp_sys = { \
371371
.analog = { \
372372
.pd_cur = PMU_PD_CUR_SLEEP_ON, \
@@ -395,7 +395,7 @@ typedef struct {
395395
pmu_hp_lp_param_t hp_lp;
396396
} pmu_sleep_param_config_t;
397397

398-
#define PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags) { \
398+
#define PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags) { \
399399
.hp_sys = { \
400400
.min_slp_slow_clk_cycle = PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES, \
401401
.analog_wait_target_cycle = PMU_HP_ANALOG_WAIT_TARGET_CYCLES, \

‎components/esp_hw_support/port/esp32c6/pmu_sleep.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -105,14 +105,14 @@ void pmu_sleep_disable_regdma_backup(void)
105105
}
106106
}
107107

108-
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
108+
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
109109
{
110110
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
111111

112112
/* LP core hardware wait time, microsecond */
113113
const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
114114
const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
115-
const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
115+
const int lp_clk_power_on_wait_time_us = (sleep_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
116116
: rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
117117

118118
const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \
@@ -158,7 +158,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
158158
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
159159
pmu_sleep_param_config_t *param,
160160
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
161-
const uint32_t pd_flags,
161+
const uint32_t sleep_flags,
162162
const uint32_t adjustment,
163163
const uint32_t slowclk_period,
164164
const uint32_t fastclk_period
@@ -172,7 +172,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
172172
param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
173173
param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
174174

175-
const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
175+
const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
176176
const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
177177
const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
178178
param->hp_sys.modem_wakeup_wait_cycle = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);

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