fix(esp_hw_support): invalidate L1DCache before enter hardware sleep

Author: esp-wzh

components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S

@@ -117,28 +117,6 @@ rv_core_critical_regs_save:
     mv      t3, t0
     csrr    t0, mscratch
     sw      t0, RV_SLP_CTX_T0(t3)
-
-    /* writeback dcache is required here!!! */
-    la      t0, CACHE_SYNC_MAP_REG
-    li      t1, 0x10                        /* map l1 dcache */
-    sw      t1, 0x0(t0)                     /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
-    la      t2, CACHE_SYNC_ADDR_REG
-    sw      zero, 0x0(t2)                   /* clear EXTMEM_CACHE_SYNC_ADDR_REG */
-    la      t0, CACHE_SYNC_SIZE_REG
-    sw      zero, 0x0(t0)                   /* clear EXTMEM_CACHE_SYNC_SIZE_REG */
-
-    la      t1, CACHE_SYNC_CTRL_REG
-    lw      t2, 0x0(t1)
-    ori     t2, t2, 0x4
-    sw      t2, 0x0(t1)
-
-    li      t0, 0x10                        /* SYNC_DONE bit */
-wait_sync_done:
-    lw      t2, 0x0(t1)
-    and     t2, t0, t2
-    beqz    t2, wait_sync_done
-
-    lw      t0, RV_SLP_CTX_T0(t3)
     lw      t1, RV_SLP_CTX_T1(t3)
     lw      t2, RV_SLP_CTX_T2(t3)
     lw      t3, RV_SLP_CTX_T3(t3)

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -12,11 +12,13 @@
 #include "esp_err.h"
 #include "esp_attr.h"
 #include "esp_private/regi2c_ctrl.h"
+#include "esp32p4/rom/cache.h"
 #include "soc/chip_revision.h"
 #include "soc/soc.h"
 #include "soc/regi2c_syspll.h"
 #include "soc/regi2c_cpll.h"
 #include "soc/rtc.h"
+#include "soc/cache_reg.h"
 #include "soc/pau_reg.h"
 #include "soc/pmu_reg.h"
 #include "soc/pmu_struct.h"
@@ -285,6 +287,11 @@ void pmu_sleep_shutdown_ldo(void) {
     CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
 }
 
+FORCE_INLINE_ATTR void sleep_writeback_l1_dcache(void) {
+    Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
+    while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE));
+}
+
 TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
 {
     lp_aon_hal_inform_wakeup_type(dslp);
@@ -297,6 +304,8 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
     pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
     pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
 
+    sleep_writeback_l1_dcache();
+
     /* Start entry into sleep mode */
     pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);