Merge branch 'espressif:release/v5.3' into release/v5.3

Jason2866 · web-flow · commit 56d82785541e · 2024-08-28T20:24:35.000+02:00
diff --git a/.gitmodules b/.gitmodules
@@ -55,6 +55,7 @@
 	sbom-url = https://github.com/DaveGamble/cJSON
 	sbom-description = Ultralightweight JSON parser in ANSI C
 	sbom-hash = acc76239bee01d8e9c858ae2cab296704e52d916
+	sbom-cve-exclude-list = CVE-2024-31755 Resolved in v1.7.18
 
 [submodule "components/mbedtls/mbedtls"]
 	path = components/mbedtls/mbedtls
diff --git a/components/bootloader_support/src/bootloader_random_esp32c6.c b/components/bootloader_support/src/bootloader_random_esp32c6.c
@@ -88,9 +88,6 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
 
-    // Revert PMU_RF_PWC_REG to it's initial value
-    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
-
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 
diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
@@ -422,7 +422,7 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit
                                &partition->pos,
                                &image_data);
         should_encrypt = (err == ESP_OK);
-#ifdef SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
+#ifdef CONFIG_SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
         if (should_encrypt) {
             // Encrypt only the app image instead of encrypting the whole partition
             size = image_data.image_len;
diff --git a/components/bt/controller/esp32c2/Kconfig.in b/components/bt/controller/esp32c2/Kconfig.in
@@ -295,12 +295,12 @@ config BT_LE_CONTROLLER_LOG_DUMP_ONLY
             Only operate in dump mode
 
 config BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
-    bool "Storage ble controller log to flash(experimental)"
+    bool "Store ble controller logs to flash(Experimental)"
     depends on !BT_LE_CONTROLLER_LOG_DUMP_ONLY
     depends on BT_LE_CONTROLLER_LOG_ENABLED
     default n
     help
-            Storage ble controller log to flash.
+            Store ble controller logs to flash memory.
 
 config BT_LE_CONTROLLER_LOG_PARTITION_SIZE
     int "size of ble controller log partition(Multiples of 4K)"
diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c
@@ -420,18 +420,19 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
 
 void esp_ble_controller_log_dump_all(bool output)
 {
+   if (log_output_mode == LOG_STORAGE_TO_FLASH) {
 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
-    esp_bt_read_ctrl_log_from_flash(output);
-#else
-    portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
-
-    portENTER_CRITICAL_SAFE(&spinlock);
-    esp_panic_handler_reconfigure_wdts(5000);
-    BT_ASSERT_PRINT("\r\n[DUMP_START:");
-    ble_log_async_output_dump_all(output);
-    BT_ASSERT_PRINT(":DUMP_END]\r\n");
-    portEXIT_CRITICAL_SAFE(&spinlock);
+        esp_bt_read_ctrl_log_from_flash(output);
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
+    } else {
+        portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
+        portENTER_CRITICAL_SAFE(&spinlock);
+        esp_panic_handler_reconfigure_wdts(5000);
+        BT_ASSERT_PRINT("\r\n[DUMP_START:");
+        ble_log_async_output_dump_all(output);
+        BT_ASSERT_PRINT(":DUMP_END]\r\n");
+        portEXIT_CRITICAL_SAFE(&spinlock);
+    }
 }
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
 
diff --git a/components/bt/controller/esp32c6/Kconfig.in b/components/bt/controller/esp32c6/Kconfig.in
@@ -343,12 +343,12 @@ config BT_LE_CONTROLLER_LOG_DUMP_ONLY
             Only operate in dump mode
 
 config BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
-    bool "Storage ble controller log to flash(experimental)"
+    bool "Store ble controller logs to flash(Experimental)"
     depends on !BT_LE_CONTROLLER_LOG_DUMP_ONLY
     depends on BT_LE_CONTROLLER_LOG_ENABLED
     default n
     help
-            Storage ble controller log to flash.
+            Store ble controller logs to flash memory.
 
 config BT_LE_CONTROLLER_LOG_PARTITION_SIZE
     int "size of ble controller log partition(Multiples of 4K)"
diff --git a/components/bt/controller/esp32h2/Kconfig.in b/components/bt/controller/esp32h2/Kconfig.in
@@ -334,12 +334,12 @@ config BT_LE_CONTROLLER_LOG_DUMP_ONLY
             Only operate in dump mode
 
 config BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
-    bool "Storage ble controller log to flash(experimental)"
+    bool "Store ble controller logs to flash(Experimental)"
     depends on !BT_LE_CONTROLLER_LOG_DUMP_ONLY
     depends on BT_LE_CONTROLLER_LOG_ENABLED
     default n
     help
-            Storage ble controller log to flash.
+            Store ble controller logs to flash memory.
 
 config BT_LE_CONTROLLER_LOG_PARTITION_SIZE
     int "size of ble controller log partition(Multiples of 4K)"
diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32
@@ -1 +1 @@
-Subproject commit b814f26bbb3d726418c0f80f9f91153dfd978f85
+Subproject commit 3bb36a79cdfad65c656b9238e0d46b935775ed72
diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib
@@ -1 +1 @@
-Subproject commit fc65dbee2093051bdf8dd45fd4346811a39a4ff8
+Subproject commit db84a7e4539c5d9e6b8ec882b82a5de0fb8400c7
diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib
@@ -1 +1 @@
-Subproject commit 2085541b6e9963640e4090401faaf2061758d847
+Subproject commit 3396205d48647372568ba67e41c4e08917ef1038
diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib
@@ -1 +1 @@
-Subproject commit 9e29a8b39fe81ac82064dc4525e56e0faa9e1b8a
+Subproject commit 85174c19ced288f48254b01957609b8423c757bf
diff --git a/components/bt/include/esp32/include/esp_bt.h b/components/bt/include/esp32/include/esp_bt.h
@@ -55,7 +55,7 @@ extern "C" {
 *
 * @note Please do not modify this value.
 */
-#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL  0x20240315
+#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL  0x20240722
 
 /**
  * @brief Bluetooth Controller mode
@@ -202,6 +202,7 @@ the adv packet will be discarded until the memory is restored. */
     .ble_sca = CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF,             \
     .pcm_role = CONFIG_BTDM_CTRL_PCM_ROLE_EFF,                             \
     .pcm_polar = CONFIG_BTDM_CTRL_PCM_POLAR_EFF,                           \
+    .pcm_fsyncshp = 0,                                                     \
     .hli = BTDM_CTRL_HLI,                                                  \
     .dup_list_refresh_period = SCAN_DUPL_CACHE_REFRESH_PERIOD,             \
     .ble_scan_backoff = BTDM_CTRL_SCAN_BACKOFF_UPPERLIMITMAX,              \
@@ -253,6 +254,7 @@ typedef struct {
     uint8_t ble_sca;                        /*!< BLE low power crystal accuracy index. Configurable in menuconfig */
     uint8_t pcm_role;                       /*!< PCM role (master & slave). Configurable in menuconfig */
     uint8_t pcm_polar;                      /*!< PCM polar trig (falling clk edge & rising clk edge). Configurable in menuconfig */
+    uint8_t pcm_fsyncshp;                   /*!< Physical shape of the PCM Frame Synchronization signal (stereo mode & mono mode). Configurable in menuconfig */
     bool hli;                               /*!< True if using high level interrupt; false otherwise. Configurable in menuconfig */
     uint16_t dup_list_refresh_period;       /*!< Scan duplicate filtering list refresh period in seconds. Configurable in menuconfig */
     bool ble_scan_backoff;                  /*!< True if BLE scan backoff is enabled; false otherwise. Configurable in menuconfig */
diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf
@@ -21,6 +21,9 @@ entries:
     rtc_time (noflash_text)
     if SOC_PMU_SUPPORTED = y:
         pmu_sleep (noflash)
+    if SPIRAM_FLASH_LOAD_TO_PSRAM = y:
+        pmu_init (noflash)
+        pmu_param (noflash)
     if SOC_USB_SERIAL_JTAG_SUPPORTED = y:
         sleep_console (noflash)
     if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
@@ -583,8 +583,6 @@ r_ble_ll_adv_scan_req_rxd = 0x40000c98;
 r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;
 r_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;
 r_ble_ll_adv_scheduled = 0x40000ca4;
-r_ble_ll_adv_set_adv_params = 0x40000cb0;
-r_ble_ll_adv_set_enable = 0x40000cb4;
 r_ble_ll_adv_set_random_addr = 0x40000cb8;
 r_ble_ll_adv_sm_deinit = 0x40000cc4;
 r_ble_ll_adv_sm_event_init = 0x40000cc8;
@@ -689,8 +687,6 @@ r_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;
 r_ble_ll_ctrl_reject_ind_send = 0x40000ec4;
 r_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;
 r_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;
-r_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;
-r_ble_ll_ctrl_rx_conn_update = 0x40000ed4;
 r_ble_ll_ctrl_rx_enc_req = 0x40000ed8;
 r_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;
 r_ble_ll_ctrl_rx_feature_req = 0x40000ee0;
@@ -780,7 +776,6 @@ r_ble_ll_hci_rd_local_version = 0x4000106c;
 r_ble_ll_hci_scan_set_enable = 0x40001070;
 r_ble_ll_hci_send_adv_report = 0x40001074;
 r_ble_ll_hci_send_dir_adv_report = 0x40001078;
-r_ble_ll_hci_send_ext_adv_report = 0x4000107c;
 r_ble_ll_hci_send_noop = 0x40001084;
 r_ble_ll_hci_set_adv_data = 0x40001088;
 r_ble_ll_hci_set_le_event_mask = 0x4000108c;
diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c
@@ -41,7 +41,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
 
 static const char *TAG = "clk";
 
-void esp_rtc_init(void)
+void IRAM_ATTR esp_rtc_init(void)
 {
 #if SOC_PMU_SUPPORTED
     pmu_init();
diff --git a/components/freertos/FreeRTOS-Kernel/sbom.yml b/components/freertos/FreeRTOS-Kernel/sbom.yml
@@ -4,3 +4,6 @@ cpe: cpe:2.3:o:amazon:freertos:{}:*:*:*:*:*:*:*
 supplier: 'Organization: Espressif Systems (Shanghai) CO LTD'
 originator: 'Organization: Amazon Web Services'
 description: An open-source, real-time operating system (RTOS) with additional features and patches from Espressif.
+cve-exclude-list:
+  - cve: CVE-2024-28115
+    reason: Affects only ARMv7-M MPU ports, and ARMv8-M ports with Memory Protected Unit (MPU) support enabled
diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
@@ -325,7 +325,7 @@ static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_
     return heap_caps_aligned_calloc(DMA_DESC_MEM_ALIGN_SIZE, num, size, caps | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
 }
 
-static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_dma_desc_num, size_t cache_line_size)
+static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_dma_desc_num)
 {
     esp_err_t ret = ESP_OK;
     for (int i = 0; i < crypto_dma_desc_num; i++) {
@@ -334,7 +334,8 @@ static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
         /*  Write back both input buffers and output buffers to clear any cache dirty bit if set
             If we want to remove `ESP_CACHE_MSYNC_FLAG_UNALIGNED` aligned flag then we need to pass
-            cache msync size = ALIGN_UP(dma_desc.size, cache_line_size), instead of dma_desc.size
+            cache msync size = ALIGN_UP(dma_desc.size, cache_line_size), where cache_line_size is the
+            the cache line size coressponding to the buffer that is being synced, instead of dma_desc.size
             Keeping the `ESP_CACHE_MSYNC_FLAG_UNALIGNED` flag just because it should not look like
             we are syncing extra bytes due to ALIGN_UP'ed size but just the number of bytes that
             are needed in the operation. */
@@ -343,7 +344,7 @@ static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_
             return ret;
         }
     }
-    ret = esp_cache_msync(dmadesc, ALIGN_UP(crypto_dma_desc_num * sizeof(crypto_dma_desc_t), cache_line_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
+    ret = esp_cache_msync(dmadesc, crypto_dma_desc_num * sizeof(crypto_dma_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
 #else
     }
 #endif
@@ -470,7 +471,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
         populated_dma_descs += (unaligned_end_bytes ? 1 : 0);
     }
 
-    if (dma_desc_link(dma_descriptors, dma_descs_needed, cache_line_size) != ESP_OK) {
+    if (dma_desc_link(dma_descriptors, dma_descs_needed) != ESP_OK) {
         ESP_LOGE(TAG, "DMA descriptors cache sync C2M failed");
         return ESP_FAIL;
     }
diff --git a/components/openthread/lib b/components/openthread/lib
@@ -1 +1 @@
-Subproject commit 34d698a274940730901b934caa023a3281aca53e
+Subproject commit 203c78501e9a6ea9ca3a929e6f9b6b9691ef16ee
diff --git a/components/openthread/src/esp_openthread_cli.c b/components/openthread/src/esp_openthread_cli.c
@@ -99,8 +99,11 @@ static void ot_cli_loop(void *context)
                     printf("Internal error: %s\n", esp_err_to_name(err));
                 }
             } else {
-                esp_openthread_cli_input(line);
-                xTaskNotifyWait(0, 0, NULL, portMAX_DELAY);
+                if (esp_openthread_cli_input(line) == ESP_OK) {
+                    xTaskNotifyWait(0, 0, NULL, portMAX_DELAY);
+                } else {
+                    printf("Openthread task is busy, failed to run command: %s\n", line);
+                }
             }
             linenoiseHistoryAdd(line);
         }
diff --git a/components/openthread/src/esp_openthread_lwip_netif.c b/components/openthread/src/esp_openthread_lwip_netif.c
@@ -23,6 +23,12 @@
 
 #define OPENTHREAD_IP6_MTU 1280
 
+#if CONFIG_OPENTHREAD_BORDER_ROUTER
+#if CONFIG_LWIP_IPV6_NUM_ADDRESSES != 12
+#error CONFIG_LWIP_IPV6_NUM_ADDRESSES should be set to 12, please configure it using `idf.py menuconfig`
+#endif
+#endif
+
 static err_t openthread_netif_init(struct netif *netif);
 static void openthread_netif_input(void *h, void *buffer, size_t len, void *eb);
 
diff --git a/components/openthread/src/esp_openthread_task_queue.c b/components/openthread/src/esp_openthread_task_queue.c
@@ -21,6 +21,8 @@ static QueueHandle_t s_task_queue = NULL;
 static int s_task_queue_event_fd = -1;
 static const char *task_queue_workflow = "task_queue";
 
+#define OT_TASK_QUEUE_SENDING_WAIT_TIME pdMS_TO_TICKS(100)
+
 typedef struct {
     esp_openthread_task_t task;
     void *arg;
@@ -60,7 +62,7 @@ esp_err_t IRAM_ATTR esp_openthread_task_queue_post(esp_openthread_task_t task, v
         ESP_RETURN_ON_FALSE_ISR(xQueueSendFromISR(s_task_queue, &task_storage, &task_woken), ESP_FAIL, OT_PLAT_LOG_TAG,
                                 "Failed to post task to OpenThread task queue");
     } else {
-        ESP_RETURN_ON_FALSE(xQueueSend(s_task_queue, &task_storage, portMAX_DELAY), ESP_FAIL, OT_PLAT_LOG_TAG,
+        ESP_RETURN_ON_FALSE(xQueueSend(s_task_queue, &task_storage, OT_TASK_QUEUE_SENDING_WAIT_TIME), ESP_FAIL, OT_PLAT_LOG_TAG,
                             "Failed to post task to OpenThread task queue");
     }
     ret = write(s_task_queue_event_fd, &val, sizeof(val));
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1319,6 +1319,10 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
     bool
     default y
 
+config SOC_SPIRAM_XIP_SUPPORTED
+    bool
+    default y
+
 config SOC_SYSTIMER_COUNTER_NUM
     int
     default 2
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -522,6 +522,9 @@
 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
 
+/*-------------------------- SPIRAM CAPS ----------------------------------------*/
+#define SOC_SPIRAM_XIP_SUPPORTED        1
+
 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
 #define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
 #define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt
@@ -33,7 +33,6 @@ api-guides/deep-sleep-stub.rst
 api-guides/blufi.rst
 api-guides/lwip.rst
 api-guides/coexist.rst
-api-guides/flash_psram_config.rst
 api-guides/usb-serial-jtag-console.rst
 api-guides/wifi.rst
 api-guides/usb-otg-console.rst
diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt
@@ -2,7 +2,6 @@ api-guides/partition-tables.rst
 api-guides/RF_calibration.rst
 api-guides/deep-sleep-stub.rst
 api-guides/coexist.rst
-api-guides/flash_psram_config.rst
 api-guides/wifi.rst
 api-guides/usb-otg-console.rst
 api-guides/esp-wifi-mesh.rst
@@ -19,7 +18,6 @@ api-reference/peripherals/usb_host/usb_host_notes_design.rst
 api-reference/peripherals/usb_host/usb_host_notes_usbh.rst
 api-reference/peripherals/usb_device.rst
 api-reference/peripherals/touch_element.rst
-api-reference/peripherals/spi_flash/xip_from_psram.inc
 api-reference/peripherals/touch_pad.rst
 api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/parlio.rst
diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst
@@ -26,7 +26,7 @@ Hardware
 
     .. only:: esp32 or esp32s2 or esp32s3
 
-        Some PSRAM chips are 1.8 V devices and some are 3.3 V. The working voltage of the PSRAM chip must match the working voltage of the flash component. Consult the datasheet for your PSRAM chip and {IDF_TARGET_NAME} device to find out the working voltages. For a 1.8 V PSRAM chip, make sure to either set the MTDI pin to a high signal level on bootup, or program {IDF_TARGET_NAME} eFuses to always use the VDD_SIO level of 1.8 V. Not doing this can damage the PSRAM and/or flash chip.
+        Some PSRAM chips are 1.8 V devices and some are 3.3 V. The working voltage of the PSRAM chip must match the working voltage of the flash component. Consult the datasheet for your PSRAM chip and {IDF_TARGET_NAME} device to find out the working voltages. For a 1.8 V PSRAM chip, make sure to either set the MTDI pin to a high signal level on boot-up, or program {IDF_TARGET_NAME} eFuses to always use the VDD_SIO level of 1.8 V. Not doing this can damage the PSRAM and/or flash chip.
 
     .. only:: esp32p4
 
@@ -55,8 +55,7 @@ ESP-IDF fully supports the use of external RAM in applications. Once the externa
     * :ref:`external_ram_config_malloc` (default)
     * :ref:`external_ram_config_bss`
     :esp32: * :ref:`external_ram_config_noinit`
-    :SOC_SPIRAM_XIP_SUPPORTED: * :ref:`external_ram_config_instructions`
-    :SOC_SPIRAM_XIP_SUPPORTED: * :ref:`external_ram_config_rodata`
+    :SOC_SPIRAM_XIP_SUPPORTED: * :ref:`external_ram_config_xip`
 
 .. _external_ram_config_memory_map:
 
@@ -139,8 +138,6 @@ Remaining external RAM can also be added to the capability heap allocator using
 
     .. only:: esp32s2 or esp32s3
 
-        .. _external_ram_config_instructions:
-
         Move Instructions in Flash to PSRAM
         -----------------------------------
 
@@ -152,8 +149,6 @@ Remaining external RAM can also be added to the capability heap allocator using
 
         - The corresponding virtual memory range of those instructions will also be re-mapped to PSRAM.
 
-        .. _external_ram_config_rodata:
-
         Move Read-Only Data in Flash to PSRAM
         ---------------------------------------
 
@@ -165,6 +160,7 @@ Remaining external RAM can also be added to the capability heap allocator using
 
         - The corresponding virtual memory range of those rodata will also be re-mapped to PSRAM.
 
+        .. _external_ram_config_xip:
 
         Execute In Place (XiP) from PSRAM
         ------------------------------------
@@ -179,10 +175,12 @@ Remaining external RAM can also be added to the capability heap allocator using
 
     .. only:: esp32p4
 
+        .. _external_ram_config_xip:
+
         Execute In Place (XiP) from PSRAM
         ------------------------------------
 
-        The :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` option enables the executable in place (XiP) from PSRAM feature. With this option sections that are normally placed in flash ,``.text`` (for instructions) and ``.rodata`` (for read only data), will be loaded in PSRAM.
+        The :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` option enables the executable in place (XiP) from PSRAM feature. With this option sections that are normally placed in flash, ``.text`` (for instructions) and ``.rodata`` (for read only data), will be loaded in PSRAM.
 
         With this option enabled, the cache will not be disabled during an SPI1 flash operation, so code that requires executing during an SPI1 flash operation does not have to be placed in internal RAM. Because P4 flash and PSRAM are using two separate SPI buses, moving flash content to PSRAM will actually increase the load of the PSRAM MSPI bus, so the exact impact on performance will be dependent on your app usage of PSRAM. For example, as the PSRAM bus speed could be much faster than flash bus speed, if the instructions and data that are used to be in flash are not accessed very frequently, you might get better performance with this option enabled. We suggest doing performance profiling to determine if enabling this option.
 
diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
@@ -19,7 +19,7 @@ The SPI0/1 bus is shared between the instruction & data cache (for firmware exec
 
 .. only:: SOC_SPIRAM_XIP_SUPPORTED
 
-    On {IDF_TARGET_NAME}, the config options :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` (disabled by default) and :ref:`CONFIG_SPIRAM_RODATA` (disabled by default) allow the cache to read/write PSRAM concurrently with SPI1 operations. See :ref:`xip_from_psram` for more details.
+    On {IDF_TARGET_NAME}, the config options :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` (disabled by default) allows the cache to read/write PSRAM concurrently with SPI1 operations. See :ref:`xip_from_psram` for more details.
 
     If these options are disabled, the caches must be disabled while reading/writing/erasing operations. There are some constraints using driver on the SPI1 bus, see :ref:`impact_disabled_cache`. These constraints will cause more IRAM/DRAM usages.
 
@@ -40,7 +40,7 @@ Under this condition, all CPUs should always execute code and access data from i
 
     .. note::
 
-        When :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and :ref:`CONFIG_SPIRAM_RODATA` are both enabled, these APIs will not disable the caches.
+        When :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` is enabled, these APIs will not disable the caches.
 
 .. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES
 
diff --git a/docs/en/api-reference/peripherals/spi_flash/xip_from_psram.inc b/docs/en/api-reference/peripherals/spi_flash/xip_from_psram.inc
diff --git a/docs/zh_CN/api-guides/external-ram.rst b/docs/zh_CN/api-guides/external-ram.rst
diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/xip_from_psram.inc b/docs/zh_CN/api-reference/peripherals/spi_flash/xip_from_psram.inc
diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/README.md b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/README.md
diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/image/Channel_Mode.png b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/image/Channel_Mode.png
diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_hf/README.md b/examples/bluetooth/bluedroid/classic_bt/hfp_hf/README.md
diff --git a/examples/openthread/ot_br/main/esp_ot_br.c b/examples/openthread/ot_br/main/esp_ot_br.c
diff --git a/examples/openthread/ot_br/sdkconfig.defaults b/examples/openthread/ot_br/sdkconfig.defaults
