Merge branch 'feat/wait_pll_stable_after_sleep_wakeup_fix_xtal_v5.4' into 'release/v5.4'

feat(esp_hw_support): wait pll stable after sleep wakeup (v5.4)

See merge request espressif/esp-idf!36018

Author: Jiang Jiang Jian

components/esp_hw_support/include/esp_private/esp_pmu.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -46,11 +46,11 @@ typedef enum {
 #define RTC_SLEEP_PD_MODEM              PMU_SLEEP_PD_MODEM      //!< Power down modem(include wifi, ble and 15.4)
 
 //These flags are not power domains, but will affect some sleep parameters
-#define RTC_SLEEP_DIG_USE_8M            BIT(16)
-#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
-#define RTC_SLEEP_NO_ULTRA_LOW          BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
-#define RTC_SLEEP_XTAL_AS_RTC_FAST      BIT(19)
-#define RTC_SLEEP_LP_PERIPH_USE_XTAL    BIT(20)
+#define RTC_SLEEP_DIG_USE_8M            BIT(27)
+#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(28)
+#define RTC_SLEEP_NO_ULTRA_LOW          BIT(29) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
+#define RTC_SLEEP_XTAL_AS_RTC_FAST      BIT(30)
+#define RTC_SLEEP_LP_PERIPH_USE_XTAL    BIT(31)
 
 #if SOC_PM_SUPPORT_EXT0_WAKEUP
 #define RTC_EXT0_TRIG_EN            PMU_EXT0_WAKEUP_EN      //!< EXT0 wakeup
@@ -205,40 +205,40 @@ bool pmu_sleep_pll_already_enabled(void);
 /**
  * @brief Calculate the LP system hardware time overhead during sleep
  *
- * @param pd_flags flags indicates the power domain that will be powered down
+ * @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
  * @param slowclk_period re-calibrated slow clock period
  * @param fastclk_period re-calibrated fast clock period
  *
  * @return hardware time overhead in us
  */
-uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
+uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
 
 /**
  * @brief Calculate the HP system hardware time overhead during sleep
  *
- * @param pd_flags flags indicates the power domain that will be powered down
+ * @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
  * @param slowclk_period re-calibrated slow clock period
  * @param fastclk_period re-calibrated fast clock period
  *
  * @return hardware time overhead in us
  */
-uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
+uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
 
 /**
  * @brief Calculate the hardware time overhead during sleep to compensate for sleep time
  *
- * @param pd_flags flags indicates the power domain that will be powered down
+ * @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
  * @param slowclk_period re-calibrated slow clock period
  * @param fastclk_period re-calibrated fast clock period
  *
  * @return hardware time overhead in us
  */
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period);
 
 /**
  * @brief Get default sleep configuration
  * @param config pmu_sleep_config instance
- * @param pd_flags flags indicates the power domain that will be powered down
+ * @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
  * @param adjustment total software and hardware time overhead
  * @param slowclk_period re-calibrated slow clock period in microseconds,
  *                       Q13.19 fixed point format
@@ -248,7 +248,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
 
  * @return hardware time overhead in us
  */
-const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t pd_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
+const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
 
 /**
  * @brief Prepare the chip to enter sleep mode

components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c

@@ -6,10 +6,12 @@
 
 #include "esp_private/sleep_clock.h"
 #include "soc/pcr_reg.h"
+#include "soc/pmu_reg.h"
 #include "soc/rtc.h"
 #include "modem/modem_syscon_reg.h"
 #include "modem/modem_lpcon_reg.h"
 #include "soc/i2c_ana_mst_reg.h"
+#include "soc/regi2c_defs.h"
 #include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"
 
@@ -18,18 +20,30 @@ static const char *TAG = "sleep_clock";
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG,  0,               PCR_AHB_DIV_NUM,      1, 0),                                     .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
-        [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1,               PCR_BUS_CLOCK_UPDATE, 1, 0),                                     .owner = ENTRY(0) | ENTRY(1) },
+        /* Enable i2c master clock */
+        [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(0),    MODEM_LPCON_CLK_CONF_REG,   MODEM_LPCON_CLK_I2C_MST_EN,     MODEM_LPCON_CLK_I2C_MST_EN_M,   1, 0), .owner = ENTRY(0) },
+        /* Start BBPLL self-calibration */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(1),    I2C_ANA_MST_ANA_CONF0_REG,  0,                              I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
+        [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(2),    I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_STOP_FORCE_LOW,   I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
+        /* Wait calibration done */
+        [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3),    I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_CAL_DONE,         I2C_MST_BBPLL_CAL_DONE,         1, 0), .owner = ENTRY(0) },
+        /* Stop BBPLL self-calibration */
+        [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(4),    I2C_ANA_MST_ANA_CONF0_REG,  0,                              I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
+        [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(5),    I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
+        /* Clock configuration retention */
+        [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6),    PMU_CLK_STATE0_REG,         PMU_STABLE_XPD_BBPLL_STATE,     PMU_STABLE_XPD_BBPLL_STATE_M,   1, 0),  .owner = ENTRY(0)},             /* Wait PMU_WAIT_XTL_STABLE done */
+        [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(7),    PCR_AHB_FREQ_CONF_REG,      0,                              PCR_AHB_DIV_NUM,                1, 0),  .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
+        [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(8),    PCR_BUS_CLK_UPDATE_REG,     1,                              PCR_BUS_CLOCK_UPDATE,           1, 0),  .owner = ENTRY(0) | ENTRY(1) },
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
-        [2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE,        DR_REG_PCR_BASE, 75,                   0, 0, 0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+        [9] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE,            DR_REG_PCR_BASE,    75, 0, 0,   0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
 #endif
     };
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
 
     const static sleep_retention_entries_config_t modem_ahb_config[] = {
-        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
-        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
+        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
     };
     err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");
@@ -41,10 +55,10 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
          * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
          * command memory */
         sleep_retention_entries_config_t bbpll_config[] = {
-            [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(5), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */
-            [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(6), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                          0xffffffff,                   1, 0), .owner = ENTRY(1) },
-            [2] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,     0x1,                          1, 0), .owner = ENTRY(1) },
-            [3] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(8), MODEM_LPCON_CLK_CONF_REG,         0,                          MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */
+            [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(6), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */
+            [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                          0xffffffff,                   1, 0), .owner = ENTRY(1) },
+            [2] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(8), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,     0x1,                          1, 0), .owner = ENTRY(1) },
+            [3] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(9), MODEM_LPCON_CLK_CONF_REG,         0,                          MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */
         };
         extern uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
         bbpll_config[1].config.write_wait.value = phy_ana_i2c_master_burst_bbpll_config();

components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c

@@ -6,6 +6,9 @@
 
 #include "esp_private/sleep_clock.h"
 #include "soc/pcr_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/regi2c_defs.h"
+#include "modem/modem_lpcon_reg.h"
 #include "modem/modem_syscon_reg.h"
 
 static const char *TAG = "sleep_clock";
@@ -15,8 +18,19 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
     #define N_REGS_PCR()    (((PCR_SRAM_POWER_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
 
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0),   DR_REG_PCR_BASE,            DR_REG_PCR_BASE,            N_REGS_PCR(),   0, 0), .owner = ENTRY(0) | ENTRY(2) },
-        [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0x1), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
+        /* Enable i2c master clock */
+        [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_PCR_LINK(0),   MODEM_LPCON_CLK_CONF_REG,   MODEM_LPCON_CLK_I2C_MST_EN,     MODEM_LPCON_CLK_I2C_MST_EN_M,   1, 0), .owner = ENTRY(0) },
+        /* Start BBPLL self-calibration */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_PCR_LINK(1),   I2C_MST_ANA_CONF0_REG,      0,                              I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
+        [2] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_PCR_LINK(2),   I2C_MST_ANA_CONF0_REG,      I2C_MST_BBPLL_STOP_FORCE_LOW,   I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
+        /* Wait calibration done */
+        [3] = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_PCR_LINK(3),   I2C_MST_ANA_CONF0_REG,      I2C_MST_BBPLL_CAL_DONE,         I2C_MST_BBPLL_CAL_DONE,         1, 0), .owner = ENTRY(0) },
+        /* Stop BBPLL self-calibration */
+        [4] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_PCR_LINK(4),   I2C_MST_ANA_CONF0_REG,      0,                              I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
+        [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_PCR_LINK(5),   I2C_MST_ANA_CONF0_REG,      I2C_MST_BBPLL_STOP_FORCE_HIGH,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
+        /* Clock configuration retention */
+        [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6),   DR_REG_PCR_BASE,            DR_REG_PCR_BASE,            N_REGS_PCR(),                   0, 0), .owner = ENTRY(0) | ENTRY(2) },
+        [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7),   PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1,                              0, 0), .owner = ENTRY(0) | ENTRY(2) },
     };
 
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);

components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c

@@ -6,26 +6,42 @@
 
 #include "esp_private/sleep_clock.h"
 #include "soc/pcr_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/regi2c_defs.h"
+#include "modem/modem_lpcon_reg.h"
 #include "modem/modem_syscon_reg.h"
 
 static const char *TAG = "sleep_clock";
 
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG,  0, PCR_AHB_DIV_NUM,      1, 0),                                      .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
-        [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0),                                      .owner = ENTRY(0) | ENTRY(1) },
+        /* Enable i2c master clock */
+        [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG,   MODEM_LPCON_CLK_I2C_MST_EN,     MODEM_LPCON_CLK_I2C_MST_EN_M,   1, 0), .owner = ENTRY(0) },
+        /* Start BBPLL self-calibration */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG,  0,                              I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
+        [2] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_STOP_FORCE_LOW,   I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
+        /* Wait calibration done */
+        [3] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_CAL_DONE,         I2C_MST_BBPLL_CAL_DONE,         1, 0), .owner = ENTRY(0) },
+        /* Stop BBPLL self-calibration */
+        [4] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG,  0,                              I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
+        [5] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
+        /* Clock configuration retention */
+        [6] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG,         PMU_STABLE_XPD_BBPLL_STATE,     PMU_STABLE_XPD_BBPLL_STATE_M,   1, 0),  .owner = ENTRY(0)},             /* Wait PMU_WAIT_XTL_STABLE done */
+        [7] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG,      0,                              PCR_AHB_DIV_NUM,                1, 0),  .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
+        [8] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG,     1,                              PCR_BUS_CLOCK_UPDATE,           1, 0),  .owner = ENTRY(0) | ENTRY(1) },
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
-        [2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE,        DR_REG_PCR_BASE, 63,     0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }
+        [9] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE,            DR_REG_PCR_BASE,    63,     0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }
 #endif
     };
 
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
 
     const static sleep_retention_entries_config_t modem_ahb_config[] = {
-        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
-        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
+        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
     };
     err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");