Merge branch 'refactor/update_lpperi_regs_for_h2_eco5_v5.3' into 'release/v5.3'

refactor(lpperi): compatible refactor for H2 ECO5 (v5.3)

See merge request espressif/esp-idf!36336

Author: suda-morris

components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

@@ -42,6 +42,7 @@
 #include "hal/lpwdt_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "soc/pmu_reg.h"
+#include "soc/lpperi_struct.h"
 #include "hal/efuse_hal.h"
 #include "modem/modem_lpcon_reg.h"
 
@@ -107,6 +108,9 @@ esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
 
+    // Assign the compatible LPPERI register address in case it is used in the bootloader
+    lpperi_compatible_reg_addr_init();
+
     bootloader_hardware_init();
     bootloader_ana_reset_config();
     bootloader_super_wdt_auto_feed();

components/esp_system/port/cpu_start.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -61,6 +61,7 @@
 #include "esp32h2/rtc.h"
 #include "esp32h2/rom/cache.h"
 #include "esp_memprot.h"
+#include "soc/lpperi_struct.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rtc.h"
 #include "esp32c2/rom/cache.h"
@@ -459,6 +460,13 @@ void IRAM_ATTR call_start_cpu0(void)
     }
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32H2
+    // Some modules' register layout are not binary compatible among the different chip revisions,
+    // they will be wrapped into a new compatible instance which will point to the correct register address according to the revision.
+    // To ensure the compatible instance is initialized before used, the initialization is done after BBS is cleared
+    lpperi_compatible_reg_addr_init();
+#endif
+
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     // It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
     do_multicore_settings();

components/hal/esp32h2/include/hal/lp_clkrst_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -63,7 +63,7 @@ static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *h
 __attribute__((always_inline))
 static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
 {
-    LPPERI.clk_en.rng_ck_en = en;
+    LPPERI.clk_en->rng_ck_en = en;
 }
 
 /// LPPERI.clk_en is a shared register, so this function must be used in an atomic way

components/hal/esp32h2/include/hal/rtc_io_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -38,8 +38,8 @@ typedef enum {
  */
 static inline void _rtcio_ll_enable_io_clock(bool enable)
 {
-    LPPERI.clk_en.lp_io_ck_en = enable;
-    while (LPPERI.clk_en.lp_io_ck_en != enable) {
+    LPPERI.clk_en->lp_io_ck_en = enable;
+    while (LPPERI.clk_en->lp_io_ck_en != enable) {
         ;
     }
 }

components/soc/CMakeLists.txt

@@ -27,6 +27,10 @@ if(target STREQUAL "esp32")
     list(APPEND srcs "${target_folder}/dport_access.c")
 endif()
 
+if(target STREQUAL "esp32h2")
+    list(APPEND srcs "${target_folder}/lpperi_struct.c")
+endif()
+
 if(CONFIG_SOC_ADC_SUPPORTED)
     list(APPEND srcs "${target_folder}/adc_periph.c")
 endif()

components/soc/esp32h2/include/soc/lpperi_reg.h

@@ -1,7 +1,7 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+/*
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
- *  SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
@@ -11,6 +11,34 @@
 extern "C" {
 #endif
 
+/** LPPERI_DATE_REG register
+ *  need_des
+ */
+#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
+/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36732976 (0x2308030);
+ *  need_des
+ */
+#define LPPERI_LPPERI_DATE    0x7FFFFFFFU
+#define LPPERI_LPPERI_DATE_M  (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
+#define LPPERI_LPPERI_DATE_V  0x7FFFFFFFU
+#define LPPERI_LPPERI_DATE_S  0
+/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LPPERI_CLK_EN    (BIT(31))
+#define LPPERI_CLK_EN_M  (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
+#define LPPERI_CLK_EN_V  0x00000001U
+#define LPPERI_CLK_EN_S  31
+
+/**
+ * @brief Get the register offset according to the register version
+ * @note  H2 ECO5 inserted a new register LPPERI_RNG_CFG_REG,
+ *        so the addressed of the rest registers are shifted 4 bytes
+ *        This macro can help to get the correct register offset according to the register version
+ */
+#define LPPERI_REG_OFFSET(offset) (REG_GET_FIELD(LPPERI_DATE_REG, LPPERI_LPPERI_DATE) >= 0x2308030 ? (offset) : (offset) - 4)
+
+
 /** LPPERI_CLK_EN_REG register
  *  need_des
  */
@@ -140,22 +168,40 @@ extern "C" {
 #define LPPERI_LP_CPU_RESET_EN_V  0x00000001U
 #define LPPERI_LP_CPU_RESET_EN_S  31
 
+/** LPPERI_RNG_CFG_REG register
+ *  need_des
+ */
+#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8)
+/** LPPERI_RNG_CFG_ENABLE : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ *  Note: this register only exist on the chips that LPPERI_LPPERI_DATE >= 0x2308030,
+ *        i.e., ESP32-H2 chip_revision >= 1.2
+ */
+#define LPPERI_RNG_CFG_ENABLE    0x00000003U
+#define LPPERI_RNG_CFG_ENABLE_M  (LPPERI_RNG_CFG_ENABLE_V << LPPERI_RNG_CFG_ENABLE_S)
+#define LPPERI_RNG_CFG_ENABLE_V  0x00000003U
+#define LPPERI_RNG_CFG_ENABLE_S  0
+
 /** LPPERI_RNG_DATA_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
+#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0xc))
 /** LPPERI_RNG_DATA : RO; bitpos: [31:0]; default: 0;
  *  need_des
  */
-#define LPPERI_RNG_DATA    0xFFFFFFFFU
-#define LPPERI_RND_GATA_M  (LPPERI_RND_GATA_V << LPPERI_RND_GATA_S)
-#define LPPERI_RND_GATA_V  0xFFFFFFFFU
-#define LPPERI_RND_GATA_S  0
+#define LPPERI_RND_DATA    0xFFFFFFFFU
+#define LPPERI_RND_DATA_M  (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
+#define LPPERI_RND_DATA_V  0xFFFFFFFFU
+#define LPPERI_RND_DATA_S  0
 
 /** LPPERI_CPU_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
+#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x10))
 /** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
  *  need_des
  */
@@ -166,8 +212,10 @@ extern "C" {
 
 /** LPPERI_BUS_TIMEOUT_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
+#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x14))
 /** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
  *  need_des
  */
@@ -192,8 +240,10 @@ extern "C" {
 
 /** LPPERI_BUS_TIMEOUT_ADDR_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
+#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x18))
 /** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
  *  need_des
  */
@@ -204,8 +254,10 @@ extern "C" {
 
 /** LPPERI_BUS_TIMEOUT_UID_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
+#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x1c))
 /** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
  *  need_des
  */
@@ -216,8 +268,10 @@ extern "C" {
 
 /** LPPERI_MEM_CTRL_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
+#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x20))
 /** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
  *  need_des
  */
@@ -256,8 +310,10 @@ extern "C" {
 
 /** LPPERI_INTERRUPT_SOURCE_REG register
  *  need_des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
+#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x24))
 /** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
  *  BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
  *  lp_io_int
@@ -269,8 +325,10 @@ extern "C" {
 
 /** LPPERI_DEBUG_SEL0_REG register
  *  need des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x24)
+#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x28))
 /** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
  *  need des
  */
@@ -302,8 +360,10 @@ extern "C" {
 
 /** LPPERI_DEBUG_SEL1_REG register
  *  need des
+ *  Note: this register address is different on different H2 revisions,
+ *        here uses LPPERI_REG_OFFSET to get the compatible offset.
  */
-#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x28)
+#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x2c))
 /** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
  *  need des
  */
@@ -312,25 +372,6 @@ extern "C" {
 #define LPPERI_DEBUG_SEL4_V  0x0000007FU
 #define LPPERI_DEBUG_SEL4_S  0
 
-/** LPPERI_DATE_REG register
- *  need_des
- */
-#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
-/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 35676464;
- *  need_des
- */
-#define LPPERI_LPPERI_DATE    0x7FFFFFFFU
-#define LPPERI_LPPERI_DATE_M  (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
-#define LPPERI_LPPERI_DATE_V  0x7FFFFFFFU
-#define LPPERI_LPPERI_DATE_S  0
-/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LPPERI_CLK_EN    (BIT(31))
-#define LPPERI_CLK_EN_M  (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
-#define LPPERI_CLK_EN_V  0x00000001U
-#define LPPERI_CLK_EN_S  31
-
 #ifdef __cplusplus
 }
 #endif