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suda-morrissuda-morris
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Merge branch 'feature/esp32p4_ppa_driver_support_v5.3' into 'release/v5.3'
feat(ppa): add PPA driver support for ESP32P4 (v5.3) See merge request espressif/esp-idf!31074
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‎components/esp_driver_ppa/CMakeLists.txt‎

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set(srcs)
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set(public_include "include")
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if(CONFIG_SOC_PPA_SUPPORTED)
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list(APPEND srcs "src/ppa_core.c"
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"src/ppa_srm.c"
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"src/ppa_blend.c"
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"src/ppa_fill.c")
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endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${public_include}
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PRIV_REQUIRES esp_mm esp_pm
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)

‎components/esp_driver_ppa/include/driver/ppa.h‎

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‎components/esp_driver_ppa/src/ppa_blend.c‎

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‎components/esp_driver_ppa/src/ppa_core.c‎

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‎components/esp_driver_ppa/src/ppa_fill.c‎

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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_check.h"
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#include "driver/ppa.h"
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#include "ppa_priv.h"
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#include "esp_private/dma2d.h"
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#include "hal/ppa_ll.h"
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#include "esp_cache.h"
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#include "esp_memory_utils.h"
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#include "soc/dma2d_channel.h"
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static const char *TAG = "ppa_fill";
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bool ppa_fill_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel_info_t *dma2d_chans, void *user_config)
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{
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assert(num_chans == 1 && dma2d_chans && user_config);
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ppa_dma2d_trans_on_picked_config_t *trans_on_picked_desc = (ppa_dma2d_trans_on_picked_config_t *)user_config;
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assert(trans_on_picked_desc->trigger_periph == DMA2D_TRIG_PERIPH_PPA_BLEND && trans_on_picked_desc->fill_desc && trans_on_picked_desc->ppa_engine);
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ppa_fill_oper_t *fill_trans_desc = (ppa_fill_oper_t *)trans_on_picked_desc->fill_desc;
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ppa_blend_engine_t *blend_engine = __containerof(trans_on_picked_desc->ppa_engine, ppa_blend_engine_t, base);
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ppa_platform_t *platform = blend_engine->base.platform;
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// Reset blending engine
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ppa_ll_blend_reset(platform->hal.dev);
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// Get the required 2D-DMA channel handles
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assert(dma2d_chans[0].dir == DMA2D_CHANNEL_DIRECTION_RX);
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dma2d_channel_handle_t dma2d_rx_chan = dma2d_chans[0].chan;
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color_space_pixel_format_t out_pixel_format = {
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.color_type_id = fill_trans_desc->out.fill_cm,
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};
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// Fill 2D-DMA descriptors
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blend_engine->dma_rx_desc->vb_size = fill_trans_desc->fill_block_h;
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blend_engine->dma_rx_desc->hb_length = fill_trans_desc->fill_block_w;
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blend_engine->dma_rx_desc->err_eof = 0;
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blend_engine->dma_rx_desc->dma2d_en = 1;
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blend_engine->dma_rx_desc->suc_eof = 1;
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blend_engine->dma_rx_desc->owner = DMA2D_DESCRIPTOR_BUFFER_OWNER_DMA;
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blend_engine->dma_rx_desc->va_size = fill_trans_desc->out.pic_h;
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blend_engine->dma_rx_desc->ha_length = fill_trans_desc->out.pic_w;
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blend_engine->dma_rx_desc->pbyte = dma2d_desc_pixel_format_to_pbyte_value(out_pixel_format);
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blend_engine->dma_rx_desc->y = fill_trans_desc->out.block_offset_y;
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blend_engine->dma_rx_desc->x = fill_trans_desc->out.block_offset_x;
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blend_engine->dma_rx_desc->mode = DMA2D_DESCRIPTOR_BLOCK_RW_MODE_SINGLE;
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blend_engine->dma_rx_desc->buffer = (void *)fill_trans_desc->out.buffer;
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blend_engine->dma_rx_desc->next = NULL;
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esp_cache_msync((void *)blend_engine->dma_rx_desc, platform->dma_desc_mem_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
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// Configure 2D-DMA channels
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dma2d_trigger_t trig_periph = {
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.periph = DMA2D_TRIG_PERIPH_PPA_BLEND,
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.periph_sel_id = SOC_DMA2D_TRIG_PERIPH_PPA_BLEND_RX,
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};
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dma2d_connect(dma2d_rx_chan, &trig_periph);
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dma2d_transfer_ability_t dma_transfer_ability = {
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.data_burst_length = fill_trans_desc->data_burst_length,
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.desc_burst_en = true,
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.mb_size = DMA2D_MACRO_BLOCK_SIZE_NONE,
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};
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dma2d_set_transfer_ability(dma2d_rx_chan, &dma_transfer_ability);
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dma2d_rx_event_callbacks_t dma_event_cbs = {
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.on_recv_eof = ppa_transaction_done_cb,
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};
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dma2d_register_rx_event_callbacks(dma2d_rx_chan, &dma_event_cbs, (void *)trans_on_picked_desc->trans_elm);
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dma2d_set_desc_addr(dma2d_rx_chan, (intptr_t)blend_engine->dma_rx_desc);
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dma2d_start(dma2d_rx_chan);
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// Configure PPA Blending engine
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ppa_ll_blend_configure_filling_block(platform->hal.dev, &fill_trans_desc->fill_argb_color, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h);
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ppa_ll_blend_set_tx_color_mode(platform->hal.dev, fill_trans_desc->out.fill_cm);
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ppa_ll_blend_start(platform->hal.dev, PPA_LL_BLEND_TRANS_MODE_FILL);
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// No need to yield
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return false;
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}
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esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config_t *config)
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{
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ESP_RETURN_ON_FALSE(ppa_client && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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ESP_RETURN_ON_FALSE(ppa_client->oper_type == PPA_OPERATION_FILL, ESP_ERR_INVALID_ARG, TAG, "client is not for fill operations");
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ESP_RETURN_ON_FALSE(config->mode <= PPA_TRANS_MODE_NON_BLOCKING, ESP_ERR_INVALID_ARG, TAG, "invalid mode");
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// out_buffer ptr cannot in flash region
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ESP_RETURN_ON_FALSE(esp_ptr_internal(config->out.buffer) || esp_ptr_external_ram(config->out.buffer), ESP_ERR_INVALID_ARG, TAG, "invalid out.buffer addr");
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uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size;
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ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0,
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ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size");
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color_space_pixel_format_t out_pixel_format = {
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.color_type_id = config->out.fill_cm,
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};
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uint32_t out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format);
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uint32_t out_pic_len = config->out.pic_w * config->out.pic_h * out_pixel_depth / 8;
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ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size");
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// To reduce complexity, color_mode, fill_block_w/h correctness are checked in their corresponding LL functions
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// Write back and invalidate necessary data (note that the window content is not continuous in the buffer)
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// Write back and invalidate buffer extended window (alignment not necessary on C2M direction, but alignment strict on M2C direction)
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uint32_t out_ext_window = (uint32_t)config->out.buffer + config->out.block_offset_y * config->out.pic_w * out_pixel_depth / 8;
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uint32_t out_ext_window_len = config->out.pic_w * config->fill_block_h * out_pixel_depth / 8;
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esp_cache_msync((void *)PPA_ALIGN_DOWN(out_ext_window, buf_alignment_size), PPA_ALIGN_UP(out_ext_window_len, buf_alignment_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
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esp_err_t ret = ESP_OK;
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ppa_trans_t *trans_elm = NULL;
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if (xQueueReceive(ppa_client->trans_elm_ptr_queue, (void *)&trans_elm, 0)) {
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dma2d_trans_config_t *dma_trans_desc = trans_elm->trans_desc;
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ppa_dma2d_trans_on_picked_config_t *trans_on_picked_desc = dma_trans_desc->user_config;
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ppa_fill_oper_t *fill_trans_desc = (ppa_fill_oper_t *)trans_on_picked_desc->fill_desc;
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memcpy(fill_trans_desc, config, sizeof(ppa_fill_oper_config_t));
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fill_trans_desc->data_burst_length = ppa_client->data_burst_length;
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trans_on_picked_desc->ppa_engine = ppa_client->engine;
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trans_on_picked_desc->trigger_periph = DMA2D_TRIG_PERIPH_PPA_BLEND;
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dma_trans_desc->tx_channel_num = 0;
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dma_trans_desc->rx_channel_num = 1;
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dma_trans_desc->channel_flags = 0;
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dma_trans_desc->specified_tx_channel_mask = 0;
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dma_trans_desc->specified_rx_channel_mask = 0;
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trans_elm->client = ppa_client;
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trans_elm->user_data = config->user_data;
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xSemaphoreTake(trans_elm->sem, 0); // Ensure no transaction semaphore before transaction starts
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ret = ppa_do_operation(ppa_client, ppa_client->engine, trans_elm, config->mode);
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if (ret != ESP_OK) {
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ppa_recycle_transaction(ppa_client, trans_elm);
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}
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} else {
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ret = ESP_FAIL;
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ESP_LOGE(TAG, "exceed maximum pending transactions for the client, consider increase max_pending_trans_num");
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}
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return ret;
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}

‎components/esp_driver_ppa/src/ppa_priv.h‎

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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <sys/queue.h>
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#include "sdkconfig.h"
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#include "driver/ppa.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "esp_private/dma2d.h"
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#include "hal/dma2d_types.h"
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#include "hal/ppa_types.h"
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#include "hal/ppa_hal.h"
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#include "esp_pm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PPA_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
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#define PPA_PM_LOCK_NAME_LEN_MAX 16
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#define PPA_CHECK_CM_SUPPORT_BYTE_SWAP(str, color_type_id) \
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ESP_RETURN_ON_FALSE(color_type_id == COLOR_TYPE_ID(COLOR_SPACE_ARGB, COLOR_PIXEL_ARGB8888) || color_type_id == COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), \
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ESP_ERR_INVALID_ARG, TAG, str "_cm does not support byte_swap");
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#define PPA_CHECK_CM_SUPPORT_RGB_SWAP(str, color_type_id) \
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ESP_RETURN_ON_FALSE(COLOR_SPACE_TYPE(color_type_id) == COLOR_SPACE_ARGB || COLOR_SPACE_TYPE(color_type_id) == COLOR_SPACE_RGB, \
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ESP_ERR_INVALID_ARG, TAG, str "_cm does not support rgb_swap");
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#define PPA_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
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#define PPA_ALIGN_DOWN(num, align) ((num) & ~((align) - 1))
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typedef struct ppa_platform_t ppa_platform_t;
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/******************************** ENGINE *************************************/
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// PPA module contains SRM engine and Blending engine
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typedef struct ppa_engine_t ppa_engine_t;
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struct ppa_engine_t {
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ppa_platform_t *platform; // PPA driver platform
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ppa_engine_type_t type; // Type of the PPA engine
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portMUX_TYPE spinlock; // Engine level spinlock
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SemaphoreHandle_t sem; // Semaphore for whether the engine is processing a transaction
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STAILQ_HEAD(trans, ppa_trans_s) trans_stailq; // link head of pending transactions for the PPA engine
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#if CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock; // Power management lock
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#endif
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};
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typedef struct ppa_srm_engine_t {
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ppa_engine_t base; // PPA engine base structure
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dma2d_descriptor_t *dma_tx_desc; // Into PPA SRM engine direction 2D-DMA descriptor
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dma2d_descriptor_t *dma_rx_desc; // Out from PPA SRM engine direction 2D-DMA descriptor
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} ppa_srm_engine_t;
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typedef struct ppa_blend_engine_t {
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ppa_engine_t base; // PPA engine base structure
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dma2d_descriptor_t *dma_tx_bg_desc; // Into PPA Blending engine direction background channel 2D-DMA descriptor
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dma2d_descriptor_t *dma_tx_fg_desc; // Into PPA Blending engine direction foreground channel 2D-DMA descriptor
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dma2d_descriptor_t *dma_rx_desc; // Out from PPA blending engine direction 2D-DMA descriptor
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} ppa_blend_engine_t;
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typedef struct {
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ppa_engine_type_t engine; // Engine type
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} ppa_engine_config_t;
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/******************************** CLIENT *************************************/
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typedef struct ppa_client_t ppa_client_t;
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struct ppa_client_t {
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ppa_operation_t oper_type; // The PPA operation type that the client wants to do in speciality
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ppa_engine_t *engine; // Pointer to the PPA engine that in charge of performing the PPA operation
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uint32_t trans_cnt; // Number of pending PPA transactions
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portMUX_TYPE spinlock; // Client level spinlock
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ppa_event_callback_t done_cb; // Transaction done callback
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QueueHandle_t trans_elm_ptr_queue; // Queue that contains the pointers to the allocated memory to save the transaction contexts
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ppa_data_burst_length_t data_burst_length; // The desired data burst length for all the transactions of the client
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};
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/****************************** OPERATION ************************************/
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// The elements in this structure listed first are identical to the elements in structure `ppa_srm_oper_config_t`
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// With adding a few extra elements at the end
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// This allows memcpy
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typedef struct {
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ppa_in_pic_blk_config_t in;
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ppa_out_pic_blk_config_t out;
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// scale-rotate-mirror manipulation
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ppa_srm_rotation_angle_t rotation_angle;
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float scale_x;
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float scale_y;
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bool mirror_x;
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bool mirror_y;
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// input data manipulation
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bool rgb_swap;
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bool byte_swap;
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ppa_alpha_update_mode_t alpha_update_mode;
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union {
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uint32_t alpha_fix_val;
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float alpha_scale_ratio;
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};
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ppa_trans_mode_t mode;
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void *user_data;
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uint32_t scale_x_int; // Calculation result for the integral part of the scale_x to be directly written to register
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uint32_t scale_x_frag; // Calculation result for the fractional part of the scale_x to be directly written to register
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uint32_t scale_y_int; // Calculation result for the integral part of the scale_y to be directly written to register
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uint32_t scale_y_frag; // Calculation result for the fractional part of the scale_y to be directly written to register
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uint32_t alpha_value; // Calculation result for the fix alpha value to be directly written to register
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ppa_data_burst_length_t data_burst_length; // Data burst length for the transaction, information passed from the client
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} ppa_srm_oper_t;
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// The elements in this structure listed first are identical to the elements in structure `ppa_blend_oper_config_t`
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// With adding a few extra elements at the end
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// This allows memcpy
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typedef struct {
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ppa_in_pic_blk_config_t in_bg;
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ppa_in_pic_blk_config_t in_fg;
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ppa_out_pic_blk_config_t out;
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// input data manipulation
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bool bg_rgb_swap;
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bool bg_byte_swap;
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ppa_alpha_update_mode_t bg_alpha_update_mode;
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union {
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uint32_t bg_alpha_fix_val;
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float bg_alpha_scale_ratio;
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};
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bool fg_rgb_swap;
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bool fg_byte_swap;
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ppa_alpha_update_mode_t fg_alpha_update_mode;
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union {
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uint32_t fg_alpha_fix_val;
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float fg_alpha_scale_ratio;
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};
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color_pixel_rgb888_data_t fg_fix_rgb_val;
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// color-keying
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bool bg_ck_en;
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color_pixel_rgb888_data_t bg_ck_rgb_low_thres;
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color_pixel_rgb888_data_t bg_ck_rgb_high_thres;
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bool fg_ck_en;
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color_pixel_rgb888_data_t fg_ck_rgb_low_thres;
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color_pixel_rgb888_data_t fg_ck_rgb_high_thres;
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color_pixel_rgb888_data_t ck_rgb_default_val;
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bool ck_reverse_bg2fg;
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ppa_trans_mode_t mode;
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void *user_data;
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uint32_t bg_alpha_value; // Calculation result for the fix alpha value for BG to be directly written to register
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uint32_t fg_alpha_value; // Calculation result for the fix alpha value for FG to be directly written to register
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ppa_data_burst_length_t data_burst_length; // Data burst length for the transaction, information passed from the client
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} ppa_blend_oper_t;
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168+
// The elements in this structure listed first are identical to the elements in structure `ppa_fill_oper_config_t`
169+
// With adding a few extra elements at the end
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// This allows memcpy
171+
typedef struct {
172+
ppa_out_pic_blk_config_t out;
173+
174+
uint32_t fill_block_w;
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uint32_t fill_block_h;
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color_pixel_argb8888_data_t fill_argb_color;
177+
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ppa_trans_mode_t mode;
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void *user_data;
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ppa_data_burst_length_t data_burst_length; // Data burst length for the transaction, information passed from the client
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} ppa_fill_oper_t;
183+
184+
/***************************** TRANSACTION ***********************************/
185+
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// PPA transaction element
187+
typedef struct ppa_trans_s {
188+
STAILQ_ENTRY(ppa_trans_s) entry; // Link entry
189+
dma2d_trans_config_t *trans_desc; // Pointer to the structure containing the configurations for a 2D-DMA transaction
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dma2d_trans_t *dma_trans_placeholder; // Pointer to the memory to store the 2D-DMA transaction context
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SemaphoreHandle_t sem; // Semaphore to block when the transaction has not finished
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ppa_client_t *client; // Pointer to the client who requested the transaction
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void *user_data; // User registered event data (per transaction)
194+
} ppa_trans_t;
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typedef struct {
197+
union {
198+
ppa_srm_oper_t *srm_desc; // Pointer to the structure containing the configurations for a PPA SRM operation transaction
199+
ppa_blend_oper_t *blend_desc; // Pointer to the structure containing the configurations for a PPA blend operation transaction
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ppa_fill_oper_t *fill_desc; // Pointer to the structure containing the configurations for a PPA fill operation transaction
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void *op_desc; // General pointer to the structure containing the configurations for a PPA transaction
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};
203+
ppa_engine_t *ppa_engine; // Pointer to the PPA engine
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ppa_trans_t *trans_elm; // Pointer to the PPA transaction element
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dma2d_trigger_peripheral_t trigger_periph; // The 2D-DMA trigger peripheral
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} ppa_dma2d_trans_on_picked_config_t;
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bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel_info_t *dma2d_chans, void *user_config);
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bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel_info_t *dma2d_chans, void *user_config);
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bool ppa_fill_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel_info_t *dma2d_chans, void *user_config);
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esp_err_t ppa_do_operation(ppa_client_handle_t ppa_client, ppa_engine_t *ppa_engine_base, ppa_trans_t *trans_elm, ppa_trans_mode_t mode);
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bool ppa_transaction_done_cb(dma2d_channel_handle_t dma2d_chan, dma2d_event_data_t *event_data, void *user_data);
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bool ppa_recycle_transaction(ppa_client_handle_t ppa_client, ppa_trans_t *trans_elm);
217+
218+
/****************************** PPA DRIVER ***********************************/
219+
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struct ppa_platform_t {
221+
_lock_t mutex; // Platform level mutex lock to protect the ppa_engine_acquire/ppa_engine_release process
222+
portMUX_TYPE spinlock; // Platform level spinlock
223+
ppa_hal_context_t hal; // PPA HAL context
224+
dma2d_pool_handle_t dma2d_pool_handle; // Pointer to the acquired 2D-DMA pool
225+
ppa_srm_engine_t *srm; // Pointer to the PPA SRM engine
226+
ppa_blend_engine_t *blending; // Pointer to the PPA blending engine
227+
uint32_t srm_engine_ref_count; // Reference count used to protect PPA SRM engine acquire and release
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uint32_t blend_engine_ref_count; // Reference count used to protect PPA blending engine acquire and release
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size_t buf_alignment_size; // Alignment requirement for the outgoing buffer addr and size to satisfy cache line size
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uint32_t dma_desc_mem_size; // Alignment requirement for the 2D-DMA descriptor to satisfy cache line size
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};
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#ifdef __cplusplus
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}
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#endif

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