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suda-morrissuda-morris
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Merge branch 'feat/esp32c5_mp_uart_support_v5.3' into 'release/v5.3'
feat(uart): support HP/LP uart on ESP32C5 MP (backport v5.3) See merge request espressif/esp-idf!31445
2 parents 8bcedab + cf123b3 commit 1056a02

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-44
lines changed

10 files changed

+96
-44
lines changed

‎components/hal/esp32c5/include/hal/uart_ll.h‎

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
112112
switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
113113
default:
114114
case 0:
115-
*source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
115+
*source_clk = (soc_module_clk_t)LP_UART_SCLK_RC_FAST;
116116
break;
117117
case 1:
118118
*source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
@@ -130,7 +130,7 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
130130
{
131131
(void)hw;
132132
switch (src_clk) {
133-
case LP_UART_SCLK_LP_FAST:
133+
case LP_UART_SCLK_RC_FAST:
134134
LP_CLKRST.lpperi.lp_uart_clk_sel = 0;
135135
break;
136136
case LP_UART_SCLK_XTAL_D2:
@@ -167,12 +167,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui
167167
// an integer part and a fractional part.
168168
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
169169
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
170-
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
171170
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
172-
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
173-
// TODO: [ESP32c5] IDF-8633 Not found sclk_div_num for LP_UART
174-
abort();
175-
#endif
176171
uart_ll_update(hw);
177172
}
178173

@@ -437,12 +432,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
437432
div_reg.val = hw->clkdiv_sync.val;
438433
int sclk_div;
439434
if ((hw) == &LP_UART) {
440-
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
441435
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
442-
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
443-
// TODO: [ESP32c5] IDF-8633 Not found sclk_div_num for LP_UART
444-
abort();
445-
#endif
446436
} else {
447437
sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
448438
}
@@ -734,7 +724,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
734724
}
735725

736726
/**
737-
* @brief Configure the transmiter to send break chars.
727+
* @brief Configure the transmitter to send break chars.
738728
*
739729
* @param hw Beginning address of the peripheral registers.
740730
* @param break_num The number of the break chars need to be send.
@@ -801,7 +791,7 @@ FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
801791
* @brief Configure the software flow control.
802792
*
803793
* @param hw Beginning address of the peripheral registers.
804-
* @param flow_ctrl The UART sofware flow control settings.
794+
* @param flow_ctrl The UART software flow control settings.
805795
* @param sw_flow_ctrl_en Set true to enable software flow control, otherwise set it false.
806796
*
807797
* @return None.
@@ -1132,7 +1122,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
11321122
* @brief Configure TX signal loop back to RX module, just for the testing purposes
11331123
*
11341124
* @param hw Beginning address of the peripheral registers.
1135-
* @param loop_back_en Set ture to enable the loop back function, else set it false.
1125+
* @param loop_back_en Set true to enable the loop back function, else set it false.
11361126
*
11371127
* @return None
11381128
*/

‎components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ extern "C" {
1919
*
2020
* 2) External 40/48MHz Crystal Clock: XTAL
2121
*
22-
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
22+
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
2323
*
2424
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
2525
* can be computed in runtime through calibration.
@@ -250,15 +250,15 @@ typedef enum {
250250
/**
251251
* @brief Array initializer for all supported clock sources of LP_UART
252252
*/
253-
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
253+
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
254254

255255
/**
256256
* @brief Type of LP_UART clock source
257257
*/
258258
typedef enum {
259-
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
259+
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */
260260
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
261-
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
261+
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is RC_FAST */
262262
} soc_periph_lp_uart_clk_src_t;
263263

264264
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

‎components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,10 @@ config SOC_FLASH_ENC_SUPPORTED
5151
bool
5252
default y
5353

54+
config SOC_LP_PERIPHERALS_SUPPORTED
55+
bool
56+
default y
57+
5458
config SOC_SPI_FLASH_SUPPORTED
5559
bool
5660
default y
@@ -383,10 +387,26 @@ config SOC_LP_UART_FIFO_LEN
383387
int
384388
default 16
385389

390+
config SOC_UART_BITRATE_MAX
391+
int
392+
default 5000000
393+
386394
config SOC_UART_SUPPORT_XTAL_CLK
387395
bool
388396
default y
389397

398+
config SOC_UART_SUPPORT_WAKEUP_INT
399+
bool
400+
default y
401+
402+
config SOC_UART_HAS_LP_UART
403+
bool
404+
default y
405+
406+
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
407+
bool
408+
default y
409+
390410
config SOC_PM_SUPPORT_MODEM_PD
391411
bool
392412
default y

‎components/soc/esp32c5/mp/include/soc/clk_tree_defs.h‎

Lines changed: 20 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -247,23 +247,39 @@ typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6)
247247

248248
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
249249

250+
/**
251+
* @brief Array initializer for all supported clock sources of UART
252+
*/
253+
#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
254+
250255
/**
251256
* @brief Type of UART clock source, reserved for the legacy UART driver
252257
*/
253-
typedef enum { // TODO: [ESP32C5] IDF-8722 (inherit from C6)
258+
typedef enum {
254259
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
255260
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
256261
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
262+
#if SOC_CLK_TREE_SUPPORTED
257263
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
264+
#else
265+
UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment*/
266+
#endif
258267
} soc_periph_uart_clk_src_legacy_t;
259268

269+
/**
270+
* @brief Array initializer for all supported clock sources of LP_UART
271+
*/
272+
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
273+
260274
/**
261275
* @brief Type of LP_UART clock source
262276
*/
263-
typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6)
264-
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
277+
typedef enum {
278+
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */
265279
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
266-
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
280+
281+
//TODO: IDF-10034
282+
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is XTAL_D2 */
267283
} soc_periph_lp_uart_clk_src_t;
268284

269285
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

‎components/soc/esp32c5/mp/include/soc/lp_uart_struct.h‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -844,7 +844,22 @@ typedef union {
844844
*/
845845
typedef union {
846846
struct {
847-
uint32_t reserved_0:24;
847+
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
848+
* The denominator of the frequency divider factor.
849+
* Only available to LP UART instance
850+
*/
851+
uint32_t sclk_div_b:6;
852+
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
853+
* The numerator of the frequency divider factor.
854+
* Only available to LP UART instance
855+
*/
856+
uint32_t sclk_div_a:6;
857+
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
858+
* The integral part of the frequency divider factor.
859+
* Only available to LP UART instance
860+
*/
861+
uint32_t sclk_div_num:8;
862+
uint32_t reserved_20:4;
848863
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
849864
* Configures whether or not to enable LP UART TX clock.\\
850865
* 0: Disable\\

‎components/soc/esp32c5/mp/include/soc/soc_caps.h‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
/*-------------------------- COMMON CAPS ---------------------------------------*/
2020
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701
2121
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725
22-
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722
22+
#define SOC_UART_SUPPORTED 1
2323
#define SOC_GDMA_SUPPORTED 1
2424
#define SOC_AHB_GDMA_SUPPORTED 1
2525
#define SOC_GPTIMER_SUPPORTED 1
@@ -60,7 +60,7 @@
6060
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
6161
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
6262
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
63-
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719
63+
#define SOC_LP_PERIPHERALS_SUPPORTED 1
6464
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
6565
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633
6666
// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8642
@@ -482,14 +482,15 @@
482482
#define SOC_UART_LP_NUM (1U)
483483
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
484484
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
485-
// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
485+
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
486486
// #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
487-
// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
487+
// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ // TODO: [ESP32C5] IDF-8642
488488
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
489-
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
489+
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
490+
#define SOC_UART_HAS_LP_UART (1) /*!< Support LP UART */
490491

491492
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
492-
// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
493+
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
493494

494495
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
495496
// #define SOC_COEX_HW_PTI (1)

‎components/soc/esp32c5/mp/include/soc/uart_channel.h‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,11 @@
88

99
#pragma once
1010

11-
// TODO: [ESP32C5] IDF-8722
12-
1311
//UART channels
14-
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
15-
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
16-
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
17-
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17
12+
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_0
13+
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 11
14+
#define UART_GPIO12_DIRECT_CHANNEL UART_NUM_0
15+
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 12
1816

19-
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
20-
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
17+
#define UART_TXD_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
18+
#define UART_RXD_GPIO12_DIRECT_CHANNEL UART_GPIO12_DIRECT_CHANNEL

‎components/soc/esp32c5/mp/include/soc/uart_pins.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,6 @@
88

99
#include "soc/io_mux_reg.h"
1010

11-
// TODO: [ESP32C5] IDF-8722
12-
1311
/* Specify the number of pins for UART */
1412
#define SOC_UART_PINS_COUNT (4)
1513

‎components/soc/esp32c5/mp/include/soc/uart_struct.h‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,7 @@ typedef union {
2020
* Represents the data UART $n read from FIFO.\\
2121
* Measurement unit: byte.
2222
*/
23-
uint32_t rxfifo_rd_byte:8;
24-
uint32_t reserved_8:24;
23+
uint32_t rxfifo_rd_byte:32;
2524
};
2625
uint32_t val;
2726
} uart_fifo_reg_t;
@@ -947,7 +946,22 @@ typedef union {
947946
*/
948947
typedef union {
949948
struct {
950-
uint32_t reserved_0:24;
949+
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
950+
* The denominator of the frequency divider factor.'
951+
* Only available to LP UART instance
952+
*/
953+
uint32_t sclk_div_b:6;
954+
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
955+
* The numerator of the frequency divider factor.
956+
* Only available to LP UART instance
957+
*/
958+
uint32_t sclk_div_a:6;
959+
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
960+
* The integral part of the frequency divider factor.
961+
* Only available to LP UART instance
962+
*/
963+
uint32_t sclk_div_num:8;
964+
uint32_t reserved_20:4;
951965
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
952966
* Configures whether or not to enable UART TX clock.\\
953967
* 0: Disable\\

‎examples/protocols/.build-test-rules.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,7 @@ examples/protocols/modbus:
184184
disable:
185185
- if: IDF_TARGET == "esp32c5"
186186
temporary: true
187-
reason: not supported yet # TODO: [ESP32C5] IDF-8722, IDF-8697
187+
reason: not supported yet # TODO: [ESP32C5] IDF-8697
188188
depends_filepatterns:
189189
- examples/common_components/protocol_examples_common/**/*
190190
- examples/protocols/modbus/mb_example_common/**/*

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