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ericlewisericlewis
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fix: rom loading
1 parent 11734e7 commit fec7173

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18 files changed

+83
-104
lines changed

18 files changed

+83
-104
lines changed

‎dist/Cores/ericlewis.Genesis/bitstream.rbf_r‎

11.3 KB
Binary file not shown.

‎dist/Cores/ericlewis.Genesis/icon.bin‎

2.53 KB
Binary file not shown.

‎src/fpga/ap_core.qsf‎

Lines changed: 19 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -705,6 +705,11 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_tx
705705
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx_disable
706706
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx
707707

708+
# set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to dram_*
709+
# set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to dram_dq[*]
710+
# set_instance_assignment -name FAST_INPUT_REGISTER ON -to dram_dq[*]
711+
# set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|dram_*
712+
708713
# start DESIGN_PARTITION(Top)
709714
# ---------------------------
710715

@@ -737,11 +742,24 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
737742

738743
# end ENTITY(mf_pllbase_0002)
739744
# ---------------------------
745+
746+
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
747+
# set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
748+
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
749+
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
750+
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
751+
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
752+
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
753+
# set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
754+
# set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
755+
# set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
756+
# set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
757+
# set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
758+
set_global_assignment -name SYSTEMVERILOG_FILE core/core_top.sv
740759
set_global_assignment -name SYSTEMVERILOG_FILE core/data_unloader.sv
741760
set_global_assignment -name SYSTEMVERILOG_FILE core/data_loader.sv
742761
set_global_assignment -name SYSTEMVERILOG_FILE core/sync_fifo.sv
743762
set_global_assignment -name SYSTEMVERILOG_FILE core/sound_i2s.sv
744-
set_global_assignment -name SYSTEMVERILOG_FILE core/core_top.sv
745763
set_global_assignment -name QIP_FILE core/rtl/T80/T80.qip
746764
set_global_assignment -name QIP_FILE core/rtl/SVP/SVP.qip
747765
set_global_assignment -name QIP_FILE core/rtl/jt89/jt89.qip
@@ -771,18 +789,5 @@ set_global_assignment -name SDC_FILE core/core_constraints.sdc
771789
set_global_assignment -name SIGNALTAP_FILE core/stp1.stp
772790
set_global_assignment -name QIP_FILE core/mf_pllbase.qip
773791
set_global_assignment -name SIP_FILE core/mf_pllbase.sip
774-
775-
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
776-
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
777-
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
778-
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
779-
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
780-
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
781-
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
782-
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
783-
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
784-
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
785-
# set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
786-
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
787792
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
788793
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎src/fpga/apf/build_id.mif‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ DATA_RADIX = HEX;
99
CONTENT
1010
BEGIN
1111

12-
0E0 : 20221006;
13-
0E1 : 00082817;
14-
0E2 : 37d387cc;
12+
0E0 : 20221008;
13+
0E1 : 00192520;
14+
0E2 : a7ba020a;
1515

1616
END;

‎src/fpga/core/core_constraints.sdc‎

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -22,14 +22,11 @@ derive_clock_uncertainty
2222
set_multicycle_path -from {ic|sdram|dout*} -to {ic|system|data*} -setup 2
2323
set_multicycle_path -from {ic|sdram|dout*} -to {ic|system|data*} -hold 1
2424

25-
set_multicycle_path -from {ic|system|data*} -to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|*[0].*|divclk}] -start -setup 2
26-
set_multicycle_path -from {ic|system|data*} -to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|*[0].*|divclk}] -start -hold 1
27-
28-
set_multicycle_path -from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|*[0].*|divclk}] -to {ic|system|data*} -setup 2
29-
set_multicycle_path -from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|*[0].*|divclk}] -to {ic|system|data*} -hold 1
30-
31-
set_multicycle_path -from {ic|system|data*} -to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk}] -start -setup 2
32-
set_multicycle_path -from {ic|system|data*} -to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk}] -start -hold 1
33-
34-
set_multicycle_path -from [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk}] -to {ic|system|data*} -setup 4
35-
set_multicycle_path -from [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|*[1].*|divclk}] -to {ic|system|data*} -hold 3
25+
set_multicycle_path -setup -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|microAddr[*]}] 2
26+
set_multicycle_path -hold -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|microAddr[*]}] 1
27+
set_multicycle_path -setup -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|nanoAddr[*]}] 2
28+
set_multicycle_path -hold -start -from [get_keepers {*fx68k:*|Ir[*]}] -to [get_keepers {*fx68k:*|nanoAddr[*]}] 1
29+
set_multicycle_path -setup -start -from [get_keepers {*|nanoLatch[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 2
30+
set_multicycle_path -hold -start -from [get_keepers {*|nanoLatch[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 1
31+
set_multicycle_path -setup -start -from [get_keepers {*|excUnit|alu|oper[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 2
32+
set_multicycle_path -hold -start -from [get_keepers {*|excUnit|alu|oper[*]}] -to [get_keepers {*|excUnit|alu|pswCcr[*]}] 1

‎src/fpga/core/core_top.sv‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -482,9 +482,9 @@ always @(posedge clk_74a) begin
482482
end
483483
32'h00000080: cs_m30_map_enable <= bridge_wr_data[0];
484484
32'h00000090: cs_menu_pause_enable <= bridge_wr_data[0];
485-
32'h00000100: lightgun_enabled <= bridge_wr_data[0];
486-
32'h00000104: show_crosshair <= bridge_wr_data[0];
487-
32'h00000108: dpad_aim_speed <= bridge_wr_data[7:0];
485+
32'h00000100: lightgun_enabled <= bridge_wr_data[0];
486+
32'h00000104: show_crosshair <= bridge_wr_data[0];
487+
32'h00000108: dpad_aim_speed <= bridge_wr_data[7:0];
488488
endcase
489489
end
490490
end
@@ -587,7 +587,7 @@ reg ioctl_wait;
587587

588588
wire cart_download;
589589

590-
synch_2 cart_download_s (
590+
synch_3 cart_download_s (
591591
ioctl_download & bridge_addr[31:28] == 4'h1,
592592
cart_download,
593593
clk_sys
@@ -653,7 +653,7 @@ data_loader #(
653653
.ADDRESS_MASK_UPPER_4(4'h1),
654654
.ADDRESS_SIZE(25),
655655
.WRITE_MEM_CLOCK_DELAY(12),
656-
.WRITE_MEM_EN_CYCLE_LENGTH(4),
656+
.WRITE_MEM_EN_CYCLE_LENGTH(2),
657657
.OUTPUT_WORD_SIZE(2)
658658
) rom_loader (
659659
.clk_74a(clk_74a),
@@ -845,13 +845,13 @@ sdram sdram
845845
.req1(rom_req),
846846
.ack1(sdrom_rdack),
847847

848-
.addr2(rom_addr2),
849-
.din2(rom_wdata),
850-
.dout2(rom_data2),
851-
.wrl2(0),
852-
.wrh2(0),
853-
.req2(rom_rd2),
854-
.ack2(rom_rdack2),
848+
// .addr2(rom_addr2),
849+
// .din2(rom_wdata),
850+
// .dout2(rom_data2),
851+
// .wrl2(0),
852+
// .wrh2(0),
853+
// .rd2(rom_rd2),
854+
// .busy2(rom_rdack2),
855855

856856
.SDRAM_DQ(dram_dq), // 16 bit bidirectional data bus
857857
.SDRAM_A(dram_a), // 13 bit multiplexed address bus
@@ -974,31 +974,31 @@ wire [31:0] cont3_key_s;
974974
wire [31:0] cont4_key_s;
975975
wire [31:0] cont1_joy_s;
976976

977-
synch_2 #(
977+
synch_3 #(
978978
.WIDTH(32)
979979
) cont1_s (
980980
cont1_key,
981981
cont1_key_s,
982982
clk_sys
983983
);
984984

985-
synch_2 #(
985+
synch_3 #(
986986
.WIDTH(32)
987987
) cont2_s (
988988
cont2_key,
989989
cont2_key_s,
990990
clk_sys
991991
);
992992

993-
synch_2 #(
993+
synch_3 #(
994994
.WIDTH(32)
995995
) cont3_s (
996996
cont3_key,
997997
cont3_key_s,
998998
clk_sys
999999
);
10001000

1001-
synch_2 #(
1001+
synch_3 #(
10021002
.WIDTH(32)
10031003
) cont4_s (
10041004
cont4_key,
@@ -1132,7 +1132,7 @@ synch_3 pause_s (
11321132
clk_sys
11331133
);
11341134

1135-
wire reset = ~reset_n | region_set;
1135+
wire reset = ~reset_n | cart_download | region_set;
11361136

11371137
system system
11381138
(

‎src/fpga/core/mf_pllbase.qip‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,7 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C
2222
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
2323
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
2424
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
25-
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
26-
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
25+
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
2726
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
2827
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
2928
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
@@ -60,9 +59,9 @@ set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_C
6059
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MjkxMDYyNzMyMA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
6160
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
6261
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::Mjc2Ljc0MDY0MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
63-
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
62+
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM="
6463
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
65-
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::OTAuMA==::UGhhc2UgU2hpZnQ="
64+
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
6665
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
6766
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
6867
set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"

‎src/fpga/core/mf_pllbase.v‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,9 @@ endmodule
8888
// Retrieval info: <generic name="gui_output_clock_frequency1" value="107.38635" />
8989
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
9090
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="276.740640 MHz" />
91-
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
91+
// Retrieval info: <generic name="gui_ps_units1" value="degrees" />
9292
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
93-
// Retrieval info: <generic name="gui_phase_shift_deg1" value="90.0" />
93+
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
9494
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
9595
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
9696
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />

‎src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
# or its authorized distributors. Please refer to the applicable
1313
# agreement for further details.
1414

15-
# ACDS 21.1 850 win32 2022.10.05.12:35:30
15+
# ACDS 21.1 850 win32 2022.10.08.09:38:40
1616
# ----------------------------------------
1717
# Auto-generated simulation script rivierapro_setup.tcl
1818
# ----------------------------------------

‎src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
# or its authorized distributors. Please refer to the applicable
1313
# agreement for further details.
1414

15-
# ACDS 21.1 850 win32 2022.10.05.12:35:30
15+
# ACDS 21.1 850 win32 2022.10.08.09:38:40
1616

1717
# ----------------------------------------
1818
# ncsim - auto-generated simulation script
@@ -106,7 +106,7 @@
106106
# within the Quartus project, and generate a unified
107107
# script which supports all the Altera IP within the design.
108108
# ----------------------------------------
109-
# ACDS 21.1 850 win32 2022.10.05.12:35:30
109+
# ACDS 21.1 850 win32 2022.10.08.09:38:40
110110
# ----------------------------------------
111111
# initialize variables
112112
TOP_LEVEL_NAME="mf_pllbase"

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