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‎dataset/testbench/hdlbits/basics1/answer_simple-wire.v‎

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module simple_wire ( input in, output out );
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assign out = in; // Simple wire connection from input to output
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// NOTE: This creates a continuous assignment (combinational logic)
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endmodule

‎dataset/testbench/hdlbits/basics1/prompt1_simple-wire.v‎

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// This is a top module with a simple wire
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module simple_wire ( input in, output out );

‎dataset/testbench/hdlbits/basics1/prompt2_simple-wire.v‎

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// This is a top module with a simple wire
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module simple_wire ( input in, output out );
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// Assign the appropriate values to one and another
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// Insert code here

‎dataset/testbench/hdlbits/basics1/prompt3_simple-wire.v‎

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// This is a top module with a simple wire
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module simple_wire ( input in, output out );
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// Assign the appropriate values to one and another
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// Assign output to input
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// Insert code here

‎dataset/testbench/hdlbits/basics1/simple_wire_tb.vcd‎

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$date
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Tue Aug 19 20:15:56 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb_top_module $end
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$var wire 1 ! out $end
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$var reg 1 " in $end
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$var reg 1 # test_passed $end
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$var integer 32 $ i [31:0] $end
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$var integer 32 % num_tests_passed [31:0] $end
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$scope module dut $end
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$var wire 1 " in $end
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$var wire 1 ! out $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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b0 %
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bx $
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1#
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x"
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x!
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$end
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#10000
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0!
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0"
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#20000
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1!
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1"
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b1 %
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#30000
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0!
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0"
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b0 $
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b10 %
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#35000
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1!
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1"
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b1 $
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b11 %
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#40000
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0!
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0"
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b10 $
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b100 %
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#45000
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1!
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1"
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b11 $
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b101 %
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#50000
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0!
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0"
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b100 $
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b110 %
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#55000
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1!
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1"
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b101 $
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b111 %
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#60000
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0!
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0"
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b110 $
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b1000 %
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#65000
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1!
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1"
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b111 $
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b1001 $
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b1 $
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#100000
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b10 $
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b1111 %
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b11 $
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b10000 %
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#110000
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0!
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b100 $
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#115000
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1!
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#120000
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b10110 %
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b10111 %
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0"
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‎dataset/testbench/hdlbits/basics1/tb_simple-wire.v‎

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`timescale 1ns/1ps
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module tb_top_module();
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// Signal to connect to DUT output
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reg in;
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wire out;
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// Instantiate the Design Under Test (DUT)
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simple_wire dut (
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.in(in), .out(out)
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);
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// Test variables
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reg test_passed;
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integer num_tests_passed;
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integer i;
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initial begin
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// Initialize test tracking
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test_passed = 1'b1;
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num_tests_passed = 0;
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// Display header
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$display("====================================");
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$display("Testing simple_wire");
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$display("====================================");
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$display("Time\tOutput\tExpected\tResult");
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$display("------------------------------------");
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// Wait for any initialization
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#10;
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// Test Case 1: Output follows input at 0
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in = 1'b0;
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#10; // Wait for propagation
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if (out == in) begin
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$display("%0t\t%b\t%b\t%b\t\tPASS", $time, in, out, in);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%0t\t%b\t%b\t%b\t\tFAIL", $time, in, out, in);
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test_passed = 1'b0;
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end
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// Test Case 2: Output follows input at 1
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in = 1'b1;
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#10;
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if (out == in) begin
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$display("%0t\t%b\t%b\t%b\t\tPASS", $time, in, out, in);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%0t\t%b\t%b\t%b\t\tFAIL", $time, in, out, in);
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test_passed = 1'b0;
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end
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// Test Case 3: Multiple transitions
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$display("\nTesting multiple transitions:");
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for (i = 0; i < 10; i = i + 1) begin
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in = ~in; // Toggle input
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#5; // Small delay
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if (out == in) begin
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$display("%0t\t%b\t%b\t%b\t\tPASS", $time, in, out, in);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%0t\t%b\t%b\t%b\t\tFAIL", $time, in, out, in);
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test_passed = 1'b0;
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end
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end
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// Test Case 3: Multiple transitions
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$display("\nTesting multiple transitions:");
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for (i = 0; i < 10; i = i + 1) begin
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in = ~in; // Toggle input
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#5; // Small delay
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if (out == in) begin
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$display("%0t\t%b\t%b\t%b\t\tPASS", $time, in, out, in);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%0t\t%b\t%b\t%b\t\tFAIL", $time, in, out, in);
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test_passed = 1'b0;
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end
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end
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// Test Case 4: Continuous monitoring
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$display("\nContinuous monitoring test:");
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fork
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begin
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// Drive random values
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repeat(20) begin
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#10 in = $random;
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end
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end
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begin
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// Monitor continuously
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repeat(20) begin
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#10;
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if (out !== in) begin
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$display("ERROR at time %0t: in=%b, out=%b", $time, in, out);
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test_passed = 1'b0;
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end
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end
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end
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join
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// Final Summary
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#10;
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$display("====================================");
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$display("Test Summary: %0d/%0d tests passed", num_tests_passed, num_tests_passed + (test_passed ? 0 : 1));
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if (test_passed)
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$display("Overall Result: ALL TESTS PASSED");
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else
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$display("Overall Result: SOME TESTS FAILED");
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$display("====================================");
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// End simulation
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#10;
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$finish;
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end
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// Optional: Generate VCD file for waveform viewing
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initial begin
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$dumpfile("simple_wire_tb.vcd");
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$dumpvars(0, tb_top_module);
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end
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endmodule

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