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noobsiecodernoobsiecoder
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added new dataset
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+435
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‎dataset/testbench/hdlbits/basics3/answer_inverter.v‎

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module not_gate ( input in, output out );
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assign out = ~in; // assign input inverted to output
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endmodule

‎dataset/testbench/hdlbits/basics3/not_gate_tb.vcd‎

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$date
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Tue Aug 19 21:01:04 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb_not_gate $end
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$var wire 1 ! out $end
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$var reg 1 " in $end
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$var integer 32 # num_tests_passed [31:0] $end
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$var integer 32 $ total_tests [31:0] $end
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$scope module dut $end
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$var wire 1 " in $end
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$var wire 1 ! out $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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b0 $
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b0 #
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0"
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1!
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$end
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#10000
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0!
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1"
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b1 $
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b1 #
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#20000
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1!
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0"
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b10 $
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b10 #
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#25000
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0!
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1"
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b11 $
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b11 #
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#30000
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1!
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0"
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b100 $
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b100 #
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#35000
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0!
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1"
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b101 $
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b101 #
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#40000
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1!
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0"
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b110 $
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b110 #
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#45000
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0!
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1"
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b111 $
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b111 #
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#50000
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1!
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0"
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b1000 $
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b1000 #
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#55000
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0!
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1"
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b1001 $
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b1001 #
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#60000
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1!
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0"
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b1010 $
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b1010 #
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#65000
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0!
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1"
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b1011 $
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b1011 #
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#70000
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b1100 $
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b1100 #

‎dataset/testbench/hdlbits/basics3/prompt1_inverter.v‎

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// This a not gate module
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module not_gate ( input in, output out);
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// Insert code here

‎dataset/testbench/hdlbits/basics3/prompt2_inverter.v‎

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// This a not gate module
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module not_gate ( input in, output out);
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// Invert input when assigning to output
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// Insert code here

‎dataset/testbench/hdlbits/basics3/prompt3_inverter.v‎

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// This a not gate module
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module not_gate ( input in, output out);
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// Invert input while assigning to output
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// Use the invert symbol (~)
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// Insert code here

‎dataset/testbench/hdlbits/basics3/tb_inverter.v‎

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`timescale 1ns/1ps
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module tb_not_gate();
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// Inputs (driven by testbench)
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reg in;
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// Outputs (driven by DUT)
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wire out;
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// Instantiate the Design Under Test (DUT)
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not_gate dut (
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.in(in),
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.out(out)
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);
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// Test variables
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integer num_tests_passed;
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integer total_tests;
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initial begin
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// Initialize test tracking
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num_tests_passed = 0;
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total_tests = 0;
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// Display header
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$display("=========================================");
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$display("Testing not_gate module");
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$display("=========================================");
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$display("Time | Input | Expected | Output | Result");
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$display("-----------------------------------------");
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// Test both possible input values (0 and 1)
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// Test 1: Input = 0
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in = 1'b0;
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#10;
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if (out == 1'b1) begin
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$display("%3t | %b | %b | %b | PASS",
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$time, in, ~in, out);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%3t | %b | %b | %b | FAIL",
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$time, in, ~in, out);
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end
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total_tests = total_tests + 1;
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// Test 2: Input = 1
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in = 1'b1;
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#10;
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if (out == 1'b0) begin
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$display("%3t | %b | %b | %b | PASS",
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$time, in, ~in, out);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%3t | %b | %b | %b | FAIL",
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$time, in, ~in, out);
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end
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total_tests = total_tests + 1;
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// Toggle test
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$display("\nToggle test:");
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repeat(10) begin
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in = ~in; // Toggle input
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#5;
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if (out == ~in) begin
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$display("%3t | %b | %b | %b | PASS",
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$time, in, ~in, out);
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num_tests_passed = num_tests_passed + 1;
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end else begin
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$display("%3t | %b | %b | %b | FAIL",
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$time, in, ~in, out);
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end
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total_tests = total_tests + 1;
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end
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// Final Summary
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$display("\n=========================================");
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$display("Test Summary: %0d/%0d tests passed", num_tests_passed, total_tests);
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if (num_tests_passed == total_tests)
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$display("Overall Result: ALL TESTS PASSED ✓");
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else
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$display("Overall Result: SOME TESTS FAILED ✗");
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$display("=========================================");
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$finish;
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end
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// Generate VCD file for waveform viewing
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initial begin
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$dumpfile("not_gate_tb.vcd");
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$dumpvars(0, tb_not_gate);
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end
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endmodule

‎dataset/testbench/hdlbits/basics3/test‎

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#! /opt/homebrew/Cellar/icarus-verilog/12.0/bin/vvp
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:ivl_version "12.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 12;
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/12.0/lib/ivl/system.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/12.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/12.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/12.0/lib/ivl/va_math.vpi";
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S_0x134704080 .scope module, "tb_not_gate" "tb_not_gate" 2 3;
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.timescale -9 -12;
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v0x6000031d4240_0 .var "in", 0 0;
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v0x6000031d42d0_0 .var/i "num_tests_passed", 31 0;
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v0x6000031d4360_0 .net "out", 0 0, L_0x6000028d07e0; 1 drivers
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v0x6000031d43f0_0 .var/i "total_tests", 31 0;
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S_0x1347041f0 .scope module, "dut" "not_gate" 2 11, 3 1 0, S_0x134704080;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "in";
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.port_info 1 /OUTPUT 1 "out";
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L_0x6000028d07e0 .functor NOT 1, v0x6000031d4240_0, C4<0>, C4<0>, C4<0>;
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v0x6000031d4120_0 .net "in", 0 0, v0x6000031d4240_0; 1 drivers
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v0x6000031d41b0_0 .net "out", 0 0, L_0x6000028d07e0; alias, 1 drivers
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.scope S_0x134704080;
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T_0 ;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x6000031d42d0_0, 0, 32;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x6000031d43f0_0, 0, 32;
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%vpi_call 2 26 "$display", "=========================================" {0 0 0};
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%vpi_call 2 27 "$display", "Testing not_gate module" {0 0 0};
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%vpi_call 2 28 "$display", "=========================================" {0 0 0};
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%vpi_call 2 29 "$display", "Time | Input | Expected | Output | Result" {0 0 0};
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%vpi_call 2 30 "$display", "-----------------------------------------" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x6000031d4240_0, 0, 1;
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%delay 10000, 0;
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%load/vec4 v0x6000031d4360_0;
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%cmpi/e 1, 0, 1;
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%jmp/0xz T_0.0, 4;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%vpi_call 2 37 "$display", "%3t | %b | %b | %b | PASS", $time, v0x6000031d4240_0, S<0,vec4,u1>, v0x6000031d4360_0 {1 0 0};
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%load/vec4 v0x6000031d42d0_0;
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%addi 1, 0, 32;
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%store/vec4 v0x6000031d42d0_0, 0, 32;
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%jmp T_0.1;
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T_0.0 ;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%vpi_call 2 41 "$display", "%3t | %b | %b | %b | FAIL", $time, v0x6000031d4240_0, S<0,vec4,u1>, v0x6000031d4360_0 {1 0 0};
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T_0.1 ;
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%load/vec4 v0x6000031d43f0_0;
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%addi 1, 0, 32;
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%store/vec4 v0x6000031d43f0_0, 0, 32;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x6000031d4240_0, 0, 1;
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%delay 10000, 0;
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%load/vec4 v0x6000031d4360_0;
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%cmpi/e 0, 0, 1;
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%jmp/0xz T_0.2, 4;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%vpi_call 2 50 "$display", "%3t | %b | %b | %b | PASS", $time, v0x6000031d4240_0, S<0,vec4,u1>, v0x6000031d4360_0 {1 0 0};
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%load/vec4 v0x6000031d42d0_0;
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%addi 1, 0, 32;
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%store/vec4 v0x6000031d42d0_0, 0, 32;
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%jmp T_0.3;
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T_0.2 ;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%vpi_call 2 54 "$display", "%3t | %b | %b | %b | FAIL", $time, v0x6000031d4240_0, S<0,vec4,u1>, v0x6000031d4360_0 {1 0 0};
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T_0.3 ;
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%load/vec4 v0x6000031d43f0_0;
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%addi 1, 0, 32;
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%store/vec4 v0x6000031d43f0_0, 0, 32;
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%vpi_call 2 60 "$display", "\012Toggle test:" {0 0 0};
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%pushi/vec4 10, 0, 32;
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T_0.4 %dup/vec4;
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%pushi/vec4 0, 0, 32;
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%cmp/s;
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%jmp/1xz T_0.5, 5;
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%jmp/1 T_0.5, 4;
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%pushi/vec4 1, 0, 32;
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%sub;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%store/vec4 v0x6000031d4240_0, 0, 1;
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%delay 5000, 0;
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%load/vec4 v0x6000031d4360_0;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%cmp/e;
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%jmp/0xz T_0.6, 4;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%vpi_call 2 66 "$display", "%3t | %b | %b | %b | PASS", $time, v0x6000031d4240_0, S<0,vec4,u1>, v0x6000031d4360_0 {1 0 0};
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%load/vec4 v0x6000031d42d0_0;
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%addi 1, 0, 32;
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%store/vec4 v0x6000031d42d0_0, 0, 32;
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%jmp T_0.7;
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T_0.6 ;
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%load/vec4 v0x6000031d4240_0;
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%inv;
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%vpi_call 2 70 "$display", "%3t | %b | %b | %b | FAIL", $time, v0x6000031d4240_0, S<0,vec4,u1>, v0x6000031d4360_0 {1 0 0};
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T_0.7 ;
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%load/vec4 v0x6000031d43f0_0;
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%addi 1, 0, 32;
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%store/vec4 v0x6000031d43f0_0, 0, 32;
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%jmp T_0.4;
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T_0.5 ;
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%pop/vec4 1;
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%vpi_call 2 77 "$display", "\012=========================================" {0 0 0};
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%vpi_call 2 78 "$display", "Test Summary: %0d/%0d tests passed", v0x6000031d42d0_0, v0x6000031d43f0_0 {0 0 0};
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%load/vec4 v0x6000031d42d0_0;
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%load/vec4 v0x6000031d43f0_0;
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%cmp/e;
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%jmp/0xz T_0.8, 4;
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%vpi_call 2 80 "$display", "Overall Result: ALL TESTS PASSED \342\234\223" {0 0 0};
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%jmp T_0.9;
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T_0.8 ;
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%vpi_call 2 82 "$display", "Overall Result: SOME TESTS FAILED \342\234\227" {0 0 0};
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T_0.9 ;
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%vpi_call 2 83 "$display", "=========================================" {0 0 0};
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%vpi_call 2 85 "$finish" {0 0 0};
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%end;
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.thread T_0;
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.scope S_0x134704080;
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T_1 ;
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%vpi_call 2 90 "$dumpfile", "not_gate_tb.vcd" {0 0 0};
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%vpi_call 2 91 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x134704080 {0 0 0};
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%end;
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.thread T_1;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"tb_inverter.v";
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"answer_inverter.v";

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